Donate to e Foundation | Murena handsets with /e/OS | Own a part of Murena! Learn more

Commit b29a6d4b authored by qctecmdr's avatar qctecmdr Committed by Gerrit - the friendly Code Review server
Browse files

Merge "ARM: dts: msm: add support for the npu clocks and bw voting"

parents 3b949b0d 44d8aa5e

qcom/lito.dtsi

+20 −6
Original line number Diff line number Diff line
@@ -3166,19 +3166,26 @@ 
		governor = "performance";

		qcom,src-dst-ports = <MSM_BUS_MASTER_NPU MSM_BUS_SLAVE_EBI_CH0>;

		operating-points-v2 = <&suspendable_ddr_bw_opp_table>;

		status = "disabled";

	};



	npu_npu_ddr_bwmon: qcom,npu-npu-ddr-bwmon@9960300 {

		compatible = "qcom,bimc-bwmon4";

		reg = <0x00060400 0x300>, <0x00060300 0x200>;

		reg-names = "base", "global_base";

		interrupts = <GIC_SPI 365 IRQ_TYPE_LEVEL_HIGH>;

		clocks = <&gcc GCC_NPU_BWMON_CFG_AHB_CLK>,

				<&gcc GCC_NPU_BWMON_AXI_CLK>,

				<&gcc GCC_NPU_BWMON2_AXI_CLK>;

		clock-names = "npu_bwmon_ahb", "npu_bwmon_axi",

				"npu_bwmon2_axi";

		qcom,bwmon_clks = "npu_bwmon_ahb", "npu_bwmon_axi",

				"npu_bwmon2_axi";

		qcom,msm_bus = <154 512>;

		qcom,msm_bus_name = "npu_bwmon_cdsp";

		interrupts = <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>;

		qcom,mport = <0>;

		qcom,hw-timer-hz = <19200000>;

		qcom,target-dev = <&npu_npu_ddr_bw>;

		qcom,count-unit = <0x10000>;

		status = "disabled";

	};



	npudsp_npu_ddr_bw: qcom,npudsp-npu-ddr-bw {
@@ -3186,19 +3193,26 @@ 
		governor = "performance";

		qcom,src-dst-ports = <MSM_BUS_MASTER_NPU MSM_BUS_SLAVE_EBI_CH0>;

		operating-points-v2 = <&suspendable_ddr_bw_opp_table>;

		status = "disabled";

	};



	npudsp_npu_ddr_bwmon: qcom,npudsp-npu-ddr-bwmon@70200 {

		compatible = "qcom,bimc-bwmon4";

		reg = <0x00070300 0x300>, <0x00070200 0x200>;

		reg-names = "base", "global_base";

		interrupts = <GIC_SPI 155 IRQ_TYPE_LEVEL_HIGH>;

		interrupts = <GIC_SPI 205 IRQ_TYPE_LEVEL_HIGH>;

		clocks = <&gcc GCC_NPU_BWMON_CFG_AHB_CLK>,

				<&gcc GCC_NPU_BWMON_AXI_CLK>,

				<&gcc GCC_NPU_BWMON2_AXI_CLK>;

		clock-names = "npu_bwmon_ahb", "npu_bwmon_axi",

				"npu_bwmon2_axi";

		qcom,bwmon_clks = "npu_bwmon_ahb", "npu_bwmon_axi",

				"npu_bwmon2_axi";

		qcom,msm_bus = <154 512>;

		qcom,msm_bus_name = "npu_bwmon_cdsp";

		qcom,mport = <0>;

		qcom,hw-timer-hz = <19200000>;

		qcom,target-dev = <&npudsp_npu_ddr_bw>;

		qcom,count-unit = <0x10000>;

		status = "disabled";

	};



	cpu0_cpu_llcc_lat: qcom,cpu0-cpu-llcc-lat {