Donate to e Foundation | Murena handsets with /e/OS | Own a part of Murena! Learn more

Commit b0da45c6 authored by Geert Uytterhoeven's avatar Geert Uytterhoeven Committed by Simon Horman
Browse files

ARM: dts: r8a73a4: Fix W=1 dtc warnings



Warning (unit_address_vs_reg): Node /cache-controller@0 has a unit name, but no reg property
Warning (unit_address_vs_reg): Node /cache-controller@1 has a unit name, but no reg property

Move the cache-controller nodes under the cpus node, and make their
unit names and reg properties match the MPIDR values.

Signed-off-by: default avatarGeert Uytterhoeven <geert+renesas@glider.be>
Signed-off-by: default avatarSimon Horman <horms+renesas@verge.net.au>
parent 33df2753
Loading
Loading
Loading
Loading
+18 −16
Original line number Diff line number Diff line
@@ -31,36 +31,38 @@
			power-domains = <&pd_a2sl>;
			next-level-cache = <&L2_CA15>;
		};
	};

	ptm {
		compatible = "arm,coresight-etm3x";
		power-domains = <&pd_d4>;
	};

	timer {
		compatible = "arm,armv7-timer";
		interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
			     <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
			     <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
			     <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>;
	};

		L2_CA15: cache-controller@0 {
			compatible = "cache";
			reg = <0>;
			clocks = <&cpg_clocks R8A73A4_CLK_Z>;
			power-domains = <&pd_a3sm>;
			cache-unified;
			cache-level = <2>;
		};

	L2_CA7: cache-controller@1 {
		L2_CA7: cache-controller@100 {
			compatible = "cache";
			reg = <0x100>;
			clocks = <&cpg_clocks R8A73A4_CLK_Z2>;
			power-domains = <&pd_a3km>;
			cache-unified;
			cache-level = <2>;
		};
	};

	ptm {
		compatible = "arm,coresight-etm3x";
		power-domains = <&pd_d4>;
	};

	timer {
		compatible = "arm,armv7-timer";
		interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
			     <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
			     <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
			     <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>;
	};

	dbsc1: memory-controller@e6790000 {
		compatible = "renesas,dbsc-r8a73a4";