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Commit 33df2753 authored by Geert Uytterhoeven's avatar Geert Uytterhoeven Committed by Simon Horman
Browse files

ARM: dts: emev2: Fix W=1 dtc warnings 



Warning (unit_address_vs_reg): Node /clocks@e0110000/iic0_sclkdiv has a reg or ranges property, but no unit name
Warning (unit_address_vs_reg): Node /clocks@e0110000/iic0_sclk has a reg or ranges property, but no unit name
Warning (unit_address_vs_reg): Node /clocks@e0110000/iic1_sclkdiv has a reg or ranges property, but no unit name
Warning (unit_address_vs_reg): Node /clocks@e0110000/iic1_sclk has a reg or ranges property, but no unit name
Warning (unit_address_vs_reg): Node /clocks@e0110000/usia_u0_sclkdiv has a reg or ranges property, but no unit name
Warning (unit_address_vs_reg): Node /clocks@e0110000/usib_u1_sclkdiv has a reg or ranges property, but no unit name
Warning (unit_address_vs_reg): Node /clocks@e0110000/usib_u2_sclkdiv has a reg or ranges property, but no unit name
Warning (unit_address_vs_reg): Node /clocks@e0110000/usib_u3_sclkdiv has a reg or ranges property, but no unit name
Warning (unit_address_vs_reg): Node /clocks@e0110000/usia_u0_sclk has a reg or ranges property, but no unit name
Warning (unit_address_vs_reg): Node /clocks@e0110000/usib_u1_sclk has a reg or ranges property, but no unit name
Warning (unit_address_vs_reg): Node /clocks@e0110000/usib_u2_sclk has a reg or ranges property, but no unit name
Warning (unit_address_vs_reg): Node /clocks@e0110000/usib_u3_sclk has a reg or ranges property, but no unit name
Warning (unit_address_vs_reg): Node /clocks@e0110000/sti_sclk has a reg or ranges property, but no unit name

Signed-off-by: default avatarGeert Uytterhoeven <geert+renesas@glider.be>
Signed-off-by: default avatarSimon Horman <horms+renesas@verge.net.au>
parent 79c530ed

arch/arm/boot/dts/emev2.dtsi

+13 −13
Original line number Diff line number Diff line
@@ -69,25 +69,25 @@ 
			clock-frequency = <32768>;

			#clock-cells = <0>;

		};

		iic0_sclkdiv: iic0_sclkdiv {

		iic0_sclkdiv: iic0_sclkdiv@624,0 {

			compatible = "renesas,emev2-smu-clkdiv";

			reg = <0x624 0>;

			clocks = <&pll3_fo>;

			#clock-cells = <0>;

		};

		iic0_sclk: iic0_sclk {

		iic0_sclk: iic0_sclk@48c,1 {

			compatible = "renesas,emev2-smu-gclk";

			reg = <0x48c 1>;

			clocks = <&iic0_sclkdiv>;

			#clock-cells = <0>;

		};

		iic1_sclkdiv: iic1_sclkdiv {

		iic1_sclkdiv: iic1_sclkdiv@624,16 {

			compatible = "renesas,emev2-smu-clkdiv";

			reg = <0x624 16>;

			clocks = <&pll3_fo>;

			#clock-cells = <0>;

		};

		iic1_sclk: iic1_sclk {

		iic1_sclk: iic1_sclk@490,1 {

			compatible = "renesas,emev2-smu-gclk";

			reg = <0x490 1>;

			clocks = <&iic1_sclkdiv>;
@@ -100,55 +100,55 @@ 
			clock-mult = <7000>;

			#clock-cells = <0>;

		};

		usia_u0_sclkdiv: usia_u0_sclkdiv {

		usia_u0_sclkdiv: usia_u0_sclkdiv@610,0 {

			compatible = "renesas,emev2-smu-clkdiv";

			reg = <0x610 0>;

			clocks = <&pll3_fo>;

			#clock-cells = <0>;

		};

		usib_u1_sclkdiv: usib_u1_sclkdiv {

		usib_u1_sclkdiv: usib_u1_sclkdiv@65c,0 {

			compatible = "renesas,emev2-smu-clkdiv";

			reg = <0x65c 0>;

			clocks = <&pll3_fo>;

			#clock-cells = <0>;

		};

		usib_u2_sclkdiv: usib_u2_sclkdiv {

		usib_u2_sclkdiv: usib_u2_sclkdiv@65c,16 {

			compatible = "renesas,emev2-smu-clkdiv";

			reg = <0x65c 16>;

			clocks = <&pll3_fo>;

			#clock-cells = <0>;

		};

		usib_u3_sclkdiv: usib_u3_sclkdiv {

		usib_u3_sclkdiv: usib_u3_sclkdiv@660,0 {

			compatible = "renesas,emev2-smu-clkdiv";

			reg = <0x660 0>;

			clocks = <&pll3_fo>;

			#clock-cells = <0>;

		};

		usia_u0_sclk: usia_u0_sclk {

		usia_u0_sclk: usia_u0_sclk@4a0,1 {

			compatible = "renesas,emev2-smu-gclk";

			reg = <0x4a0 1>;

			clocks = <&usia_u0_sclkdiv>;

			#clock-cells = <0>;

		};

		usib_u1_sclk: usib_u1_sclk {

		usib_u1_sclk: usib_u1_sclk@4b8,1 {

			compatible = "renesas,emev2-smu-gclk";

			reg = <0x4b8 1>;

			clocks = <&usib_u1_sclkdiv>;

			#clock-cells = <0>;

		};

		usib_u2_sclk: usib_u2_sclk {

		usib_u2_sclk: usib_u2_sclk@4bc,1 {

			compatible = "renesas,emev2-smu-gclk";

			reg = <0x4bc 1>;

			clocks = <&usib_u2_sclkdiv>;

			#clock-cells = <0>;

		};

		usib_u3_sclk: usib_u3_sclk {

		usib_u3_sclk: usib_u3_sclk@4c0,1 {

			compatible = "renesas,emev2-smu-gclk";

			reg = <0x4c0 1>;

			clocks = <&usib_u3_sclkdiv>;

			#clock-cells = <0>;

		};

		sti_sclk: sti_sclk {

		sti_sclk: sti_sclk@528,1 {

			compatible = "renesas,emev2-smu-gclk";

			reg = <0x528 1>;

			clocks = <&c32ki>;