iio: adc: Increase VADC polling delay for EOC to 300ms

Typically, after requesting a conversion, VADC driver waits for
100ms for end of conversion (EOC) interrupt and in case interrupt
is not received, it polls for EOC status bit to be set, for 50ms.
If QG ESR measurement (with higher priority than SW requests) is
done, ADC is occupied for near 200ms, causing any concurrent
SW reads to time out.

Increase polling delay after waiting for EOC interrupt to 300ms
to ensure enough time for SW reads to complete.

Change-Id: I027d4c363d7ffd19d394353dee7b9d4f764d02c5
Signed-off-by: Jishnu Prakash <jprakash@codeaurora.org>