Donate to e Foundation | Murena handsets with /e/OS | Own a part of Murena! Learn more

Commit ad21b115 authored by Linus Torvalds's avatar Linus Torvalds
Browse files

Merge branch 'drm-intel-fixes' of git://git.kernel.org/pub/scm/linux/kernel/git/keithp/linux-2.6 

* 'drm-intel-fixes' of git://git.kernel.org/pub/scm/linux/kernel/git/keithp/linux-2.6:
  drm/i915: Fix unfenced alignment on pre-G33 hardware
  drm/i915: Add quirk to disable SSC on Lenovo U160 LVDS
parents b91da88f e28f8711

drivers/gpu/drm/i915/i915_drv.h

+4 −1
Original line number Diff line number Diff line
@@ -262,6 +262,7 @@ enum intel_pch { 
};



#define QUIRK_PIPEA_FORCE (1<<0)

#define QUIRK_LVDS_SSC_DISABLE (1<<1)



struct intel_fbdev;
@@ -1194,7 +1195,9 @@ void i915_gem_free_all_phys_object(struct drm_device *dev); 
void i915_gem_release(struct drm_device *dev, struct drm_file *file);



uint32_t

i915_gem_get_unfenced_gtt_alignment(struct drm_i915_gem_object *obj);

i915_gem_get_unfenced_gtt_alignment(struct drm_device *dev,

				    uint32_t size,

				    int tiling_mode);



/* i915_gem_gtt.c */

void i915_gem_restore_gtt_mappings(struct drm_device *dev);

drivers/gpu/drm/i915/i915_gem.c

+35 −36
Original line number Diff line number Diff line
@@ -1374,25 +1374,24 @@ i915_gem_free_mmap_offset(struct drm_i915_gem_object *obj) 
}



static uint32_t

i915_gem_get_gtt_size(struct drm_i915_gem_object *obj)

i915_gem_get_gtt_size(struct drm_device *dev, uint32_t size, int tiling_mode)

{

	struct drm_device *dev = obj->base.dev;

	uint32_t size;

	uint32_t gtt_size;



	if (INTEL_INFO(dev)->gen >= 4 ||

	    obj->tiling_mode == I915_TILING_NONE)

		return obj->base.size;

	    tiling_mode == I915_TILING_NONE)

		return size;



	/* Previous chips need a power-of-two fence region when tiling */

	if (INTEL_INFO(dev)->gen == 3)

		size = 1024*1024;

		gtt_size = 1024*1024;

	else

		size = 512*1024;

		gtt_size = 512*1024;



	while (size < obj->base.size)

		size <<= 1;

	while (gtt_size < size)

		gtt_size <<= 1;



	return size;

	return gtt_size;

}



/**
@@ -1403,59 +1402,52 @@ i915_gem_get_gtt_size(struct drm_i915_gem_object *obj) 
 * potential fence register mapping.

 */

static uint32_t

i915_gem_get_gtt_alignment(struct drm_i915_gem_object *obj)

i915_gem_get_gtt_alignment(struct drm_device *dev,

			   uint32_t size,

			   int tiling_mode)

{

	struct drm_device *dev = obj->base.dev;



	/*

	 * Minimum alignment is 4k (GTT page size), but might be greater

	 * if a fence register is needed for the object.

	 */

	if (INTEL_INFO(dev)->gen >= 4 ||

	    obj->tiling_mode == I915_TILING_NONE)

	    tiling_mode == I915_TILING_NONE)

		return 4096;



	/*

	 * Previous chips need to be aligned to the size of the smallest

	 * fence register that can contain the object.

	 */

	return i915_gem_get_gtt_size(obj);

	return i915_gem_get_gtt_size(dev, size, tiling_mode);

}



/**

 * i915_gem_get_unfenced_gtt_alignment - return required GTT alignment for an

 *					 unfenced object

 * @obj: object to check

 * @dev: the device

 * @size: size of the object

 * @tiling_mode: tiling mode of the object

 *

 * Return the required GTT alignment for an object, only taking into account

 * unfenced tiled surface requirements.

 */

uint32_t

i915_gem_get_unfenced_gtt_alignment(struct drm_i915_gem_object *obj)

i915_gem_get_unfenced_gtt_alignment(struct drm_device *dev,

				    uint32_t size,

				    int tiling_mode)

{

	struct drm_device *dev = obj->base.dev;

	int tile_height;



	/*

	 * Minimum alignment is 4k (GTT page size) for sane hw.

	 */

	if (INTEL_INFO(dev)->gen >= 4 || IS_G33(dev) ||

	    obj->tiling_mode == I915_TILING_NONE)

	    tiling_mode == I915_TILING_NONE)

		return 4096;



	/*

	 * Older chips need unfenced tiled buffers to be aligned to the left

	 * edge of an even tile row (where tile rows are counted as if the bo is

	 * placed in a fenced gtt region).

	/* Previous hardware however needs to be aligned to a power-of-two

	 * tile height. The simplest method for determining this is to reuse

	 * the power-of-tile object size.

	 */

	if (IS_GEN2(dev))

		tile_height = 16;

	else if (obj->tiling_mode == I915_TILING_Y && HAS_128_BYTE_Y_TILING(dev))

		tile_height = 32;

	else

		tile_height = 8;



	return tile_height * obj->stride * 2;

	return i915_gem_get_gtt_size(dev, size, tiling_mode);

}



int
@@ -2744,9 +2736,16 @@ i915_gem_object_bind_to_gtt(struct drm_i915_gem_object *obj, 
		return -EINVAL;

	}



	fence_size = i915_gem_get_gtt_size(obj);

	fence_alignment = i915_gem_get_gtt_alignment(obj);

	unfenced_alignment = i915_gem_get_unfenced_gtt_alignment(obj);

	fence_size = i915_gem_get_gtt_size(dev,

					   obj->base.size,

					   obj->tiling_mode);

	fence_alignment = i915_gem_get_gtt_alignment(dev,

						     obj->base.size,

						     obj->tiling_mode);

	unfenced_alignment =

		i915_gem_get_unfenced_gtt_alignment(dev,

						    obj->base.size,

						    obj->tiling_mode);



	if (alignment == 0)

		alignment = map_and_fenceable ? fence_alignment :

drivers/gpu/drm/i915/i915_gem_tiling.c

+3 −1
Original line number Diff line number Diff line
@@ -348,7 +348,9 @@ i915_gem_set_tiling(struct drm_device *dev, void *data, 
		/* Rebind if we need a change of alignment */

		if (!obj->map_and_fenceable) {

			u32 unfenced_alignment =

				i915_gem_get_unfenced_gtt_alignment(obj);

				i915_gem_get_unfenced_gtt_alignment(dev,

								    obj->base.size,

								    args->tiling_mode);

			if (obj->gtt_offset & (unfenced_alignment - 1))

				ret = i915_gem_object_unbind(obj);

		}

drivers/gpu/drm/i915/intel_display.c

+14 −1
Original line number Diff line number Diff line
@@ -4305,7 +4305,8 @@ static void intel_update_watermarks(struct drm_device *dev) 


static inline bool intel_panel_use_ssc(struct drm_i915_private *dev_priv)

{

	return dev_priv->lvds_use_ssc && i915_panel_use_ssc;

	return dev_priv->lvds_use_ssc && i915_panel_use_ssc

		&& !(dev_priv->quirks & QUIRK_LVDS_SSC_DISABLE);

}



static int i9xx_crtc_mode_set(struct drm_crtc *crtc,
@@ -7810,6 +7811,15 @@ static void quirk_pipea_force (struct drm_device *dev) 
	DRM_DEBUG_DRIVER("applying pipe a force quirk\n");

}



/*

 * Some machines (Lenovo U160) do not work with SSC on LVDS for some reason

 */

static void quirk_ssc_force_disable(struct drm_device *dev)

{

	struct drm_i915_private *dev_priv = dev->dev_private;

	dev_priv->quirks |= QUIRK_LVDS_SSC_DISABLE;

}



struct intel_quirk {

	int device;

	int subsystem_vendor;
@@ -7838,6 +7848,9 @@ struct intel_quirk intel_quirks[] = { 
	/* 855 & before need to leave pipe A & dpll A up */

	{ 0x3582, PCI_ANY_ID, PCI_ANY_ID, quirk_pipea_force },

	{ 0x2562, PCI_ANY_ID, PCI_ANY_ID, quirk_pipea_force },



	/* Lenovo U160 cannot use SSC on LVDS */

	{ 0x0046, 0x17aa, 0x3920, quirk_ssc_force_disable },

};



static void intel_init_quirks(struct drm_device *dev)