msm: camera: cdm: Avoid submitting BL if FIFO is full
Check for available slots in FIFO before submitting
gen_irq and debug_gen_irq BL.
CRs-Fixed: 2747279
Change-Id: Iff47aa861f13221e5295d9a3f3521a2514351933
Signed-off-by:
Alok Chauhan <alokc@codeaurora.org>
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