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Commit aa529a8d authored by Jordan Crouse's avatar Jordan Crouse
Browse files

msm: kgsl: Move hardware clock gating tables to the GPU description 



Instead of spreading the hardware clock gating tables all over the
code, move them to the master GPU list. This helps to reduce the
number of different locations in the code that need to be updated
for new targets.

Change-Id: Ic0dedbad267db453d68b5166df1a083cc5916999
Signed-off-by: default avatarJordan Crouse <jcrouse@codeaurora.org>
parent 9f0d1ff3

drivers/gpu/msm/adreno-gpulist.h

+765 −0

File changed.

Preview size limit exceeded, changes collapsed.

drivers/gpu/msm/adreno.h

+10 −0
Original line number Diff line number Diff line
@@ -336,6 +336,16 @@ struct adreno_device_private { 
	struct list_head perfcounter_list;

};



/**

 * struct adreno_reglist - simple container for register offsets / values

 */

struct adreno_reglist {

	/** @offset: Offset of the register */

	u32 offset;

	/** @value: Default value of the register to write */

	u32 value;

};



/**

 * struct adreno_gpu_core - A specific GPU core definition

 * @gpurev: Unique GPU revision identifier

drivers/gpu/msm/adreno_a5xx.c

+5 −386
Original line number Diff line number Diff line
@@ -799,399 +799,18 @@ static int a5xx_gpmu_start(struct adreno_device *adreno_dev) 
	return ret;

}



struct kgsl_hwcg_reg {

	unsigned int off;

	unsigned int val;

};



static const struct kgsl_hwcg_reg a50x_hwcg_regs[] = {

	{A5XX_RBBM_CLOCK_CNTL_SP0, 0x02222222},

	{A5XX_RBBM_CLOCK_CNTL2_SP0, 0x02222220},

	{A5XX_RBBM_CLOCK_HYST_SP0, 0x0000F3CF},

	{A5XX_RBBM_CLOCK_DELAY_SP0, 0x00000080},

	{A5XX_RBBM_CLOCK_CNTL_TP0, 0x22222222},

	{A5XX_RBBM_CLOCK_CNTL2_TP0, 0x22222222},

	{A5XX_RBBM_CLOCK_CNTL3_TP0, 0x00002222},

	{A5XX_RBBM_CLOCK_HYST_TP0, 0x77777777},

	{A5XX_RBBM_CLOCK_HYST2_TP0, 0x77777777},

	{A5XX_RBBM_CLOCK_HYST3_TP0, 0x00007777},

	{A5XX_RBBM_CLOCK_DELAY_TP0, 0x11111111},

	{A5XX_RBBM_CLOCK_DELAY2_TP0, 0x11111111},

	{A5XX_RBBM_CLOCK_DELAY3_TP0, 0x00001111},

	{A5XX_RBBM_CLOCK_CNTL2_UCHE, 0x22222222},

	{A5XX_RBBM_CLOCK_CNTL3_UCHE, 0x22222222},

	{A5XX_RBBM_CLOCK_CNTL4_UCHE, 0x00222222},

	{A5XX_RBBM_CLOCK_CNTL_UCHE, 0x22222222},

	{A5XX_RBBM_CLOCK_HYST_UCHE, 0x00FFFFF4},

	{A5XX_RBBM_CLOCK_DELAY_UCHE, 0x00000002},

	{A5XX_RBBM_CLOCK_CNTL_RB0, 0x22222222},

	{A5XX_RBBM_CLOCK_CNTL2_RB0, 0x00222222},

	{A5XX_RBBM_CLOCK_CNTL_CCU0, 0x00022220},

	{A5XX_RBBM_CLOCK_CNTL_RAC, 0x05522222},

	{A5XX_RBBM_CLOCK_CNTL2_RAC, 0x00505555},

	{A5XX_RBBM_CLOCK_HYST_RB_CCU0, 0x04040404},

	{A5XX_RBBM_CLOCK_HYST_RAC, 0x07444044},

	{A5XX_RBBM_CLOCK_DELAY_RB_CCU_L1_0, 0x00000002},

	{A5XX_RBBM_CLOCK_DELAY_RAC, 0x00010011},

	{A5XX_RBBM_CLOCK_CNTL_TSE_RAS_RBBM, 0x04222222},

	{A5XX_RBBM_CLOCK_MODE_GPC, 0x02222222},

	{A5XX_RBBM_CLOCK_MODE_VFD, 0x00002222},

	{A5XX_RBBM_CLOCK_HYST_TSE_RAS_RBBM, 0x00000000},

	{A5XX_RBBM_CLOCK_HYST_GPC, 0x04104004},

	{A5XX_RBBM_CLOCK_HYST_VFD, 0x00000000},

	{A5XX_RBBM_CLOCK_DELAY_HLSQ, 0x00000000},

	{A5XX_RBBM_CLOCK_DELAY_TSE_RAS_RBBM, 0x00004000},

	{A5XX_RBBM_CLOCK_DELAY_GPC, 0x00000200},

	{A5XX_RBBM_CLOCK_DELAY_VFD, 0x00002222}

};



static const struct kgsl_hwcg_reg a510_hwcg_regs[] = {

	{A5XX_RBBM_CLOCK_CNTL_SP0, 0x02222222},

	{A5XX_RBBM_CLOCK_CNTL_SP1, 0x02222222},

	{A5XX_RBBM_CLOCK_CNTL2_SP0, 0x02222220},

	{A5XX_RBBM_CLOCK_CNTL2_SP1, 0x02222220},

	{A5XX_RBBM_CLOCK_HYST_SP0, 0x0000F3CF},

	{A5XX_RBBM_CLOCK_HYST_SP1, 0x0000F3CF},

	{A5XX_RBBM_CLOCK_DELAY_SP0, 0x00000080},

	{A5XX_RBBM_CLOCK_DELAY_SP1, 0x00000080},

	{A5XX_RBBM_CLOCK_CNTL_TP0, 0x22222222},

	{A5XX_RBBM_CLOCK_CNTL_TP1, 0x22222222},

	{A5XX_RBBM_CLOCK_CNTL2_TP0, 0x22222222},

	{A5XX_RBBM_CLOCK_CNTL2_TP1, 0x22222222},

	{A5XX_RBBM_CLOCK_CNTL3_TP0, 0x00002222},

	{A5XX_RBBM_CLOCK_CNTL3_TP1, 0x00002222},

	{A5XX_RBBM_CLOCK_HYST_TP0, 0x77777777},

	{A5XX_RBBM_CLOCK_HYST_TP1, 0x77777777},

	{A5XX_RBBM_CLOCK_HYST2_TP0, 0x77777777},

	{A5XX_RBBM_CLOCK_HYST2_TP1, 0x77777777},

	{A5XX_RBBM_CLOCK_HYST3_TP0, 0x00007777},

	{A5XX_RBBM_CLOCK_HYST3_TP1, 0x00007777},

	{A5XX_RBBM_CLOCK_DELAY_TP0, 0x11111111},

	{A5XX_RBBM_CLOCK_DELAY_TP1, 0x11111111},

	{A5XX_RBBM_CLOCK_DELAY2_TP0, 0x11111111},

	{A5XX_RBBM_CLOCK_DELAY2_TP1, 0x11111111},

	{A5XX_RBBM_CLOCK_DELAY3_TP0, 0x00001111},

	{A5XX_RBBM_CLOCK_DELAY3_TP1, 0x00001111},

	{A5XX_RBBM_CLOCK_CNTL_UCHE, 0x22222222},

	{A5XX_RBBM_CLOCK_CNTL2_UCHE, 0x22222222},

	{A5XX_RBBM_CLOCK_CNTL3_UCHE, 0x22222222},

	{A5XX_RBBM_CLOCK_CNTL4_UCHE, 0x00222222},

	{A5XX_RBBM_CLOCK_HYST_UCHE, 0x00444444},

	{A5XX_RBBM_CLOCK_DELAY_UCHE, 0x00000002},

	{A5XX_RBBM_CLOCK_CNTL_RB0, 0x22222222},

	{A5XX_RBBM_CLOCK_CNTL_RB1, 0x22222222},

	{A5XX_RBBM_CLOCK_CNTL2_RB0, 0x00222222},

	{A5XX_RBBM_CLOCK_CNTL2_RB1, 0x00222222},

	{A5XX_RBBM_CLOCK_CNTL_CCU0, 0x00022220},

	{A5XX_RBBM_CLOCK_CNTL_CCU1, 0x00022220},

	{A5XX_RBBM_CLOCK_CNTL_RAC, 0x05522222},

	{A5XX_RBBM_CLOCK_CNTL2_RAC, 0x00505555},

	{A5XX_RBBM_CLOCK_HYST_RB_CCU0, 0x04040404},

	{A5XX_RBBM_CLOCK_HYST_RB_CCU1, 0x04040404},

	{A5XX_RBBM_CLOCK_HYST_RAC, 0x07444044},

	{A5XX_RBBM_CLOCK_DELAY_RB_CCU_L1_0, 0x00000002},

	{A5XX_RBBM_CLOCK_DELAY_RB_CCU_L1_1, 0x00000002},

	{A5XX_RBBM_CLOCK_DELAY_RAC, 0x00010011},

	{A5XX_RBBM_CLOCK_CNTL_TSE_RAS_RBBM, 0x04222222},

	{A5XX_RBBM_CLOCK_MODE_GPC, 0x02222222},

	{A5XX_RBBM_CLOCK_MODE_VFD, 0x00002222},

	{A5XX_RBBM_CLOCK_HYST_TSE_RAS_RBBM, 0x00000000},

	{A5XX_RBBM_CLOCK_HYST_GPC, 0x04104004},

	{A5XX_RBBM_CLOCK_HYST_VFD, 0x00000000},

	{A5XX_RBBM_CLOCK_DELAY_HLSQ, 0x00000000},

	{A5XX_RBBM_CLOCK_DELAY_TSE_RAS_RBBM, 0x00004000},

	{A5XX_RBBM_CLOCK_DELAY_GPC, 0x00000200},

	{A5XX_RBBM_CLOCK_DELAY_VFD, 0x00002222}

};



static const struct kgsl_hwcg_reg a530_hwcg_regs[] = {

	{A5XX_RBBM_CLOCK_CNTL_SP0, 0x02222222},

	{A5XX_RBBM_CLOCK_CNTL_SP1, 0x02222222},

	{A5XX_RBBM_CLOCK_CNTL_SP2, 0x02222222},

	{A5XX_RBBM_CLOCK_CNTL_SP3, 0x02222222},

	{A5XX_RBBM_CLOCK_CNTL2_SP0, 0x02222220},

	{A5XX_RBBM_CLOCK_CNTL2_SP1, 0x02222220},

	{A5XX_RBBM_CLOCK_CNTL2_SP2, 0x02222220},

	{A5XX_RBBM_CLOCK_CNTL2_SP3, 0x02222220},

	{A5XX_RBBM_CLOCK_HYST_SP0, 0x0000F3CF},

	{A5XX_RBBM_CLOCK_HYST_SP1, 0x0000F3CF},

	{A5XX_RBBM_CLOCK_HYST_SP2, 0x0000F3CF},

	{A5XX_RBBM_CLOCK_HYST_SP3, 0x0000F3CF},

	{A5XX_RBBM_CLOCK_DELAY_SP0, 0x00000080},

	{A5XX_RBBM_CLOCK_DELAY_SP1, 0x00000080},

	{A5XX_RBBM_CLOCK_DELAY_SP2, 0x00000080},

	{A5XX_RBBM_CLOCK_DELAY_SP3, 0x00000080},

	{A5XX_RBBM_CLOCK_CNTL_TP0, 0x22222222},

	{A5XX_RBBM_CLOCK_CNTL_TP1, 0x22222222},

	{A5XX_RBBM_CLOCK_CNTL_TP2, 0x22222222},

	{A5XX_RBBM_CLOCK_CNTL_TP3, 0x22222222},

	{A5XX_RBBM_CLOCK_CNTL2_TP0, 0x22222222},

	{A5XX_RBBM_CLOCK_CNTL2_TP1, 0x22222222},

	{A5XX_RBBM_CLOCK_CNTL2_TP2, 0x22222222},

	{A5XX_RBBM_CLOCK_CNTL2_TP3, 0x22222222},

	{A5XX_RBBM_CLOCK_CNTL3_TP0, 0x00002222},

	{A5XX_RBBM_CLOCK_CNTL3_TP1, 0x00002222},

	{A5XX_RBBM_CLOCK_CNTL3_TP2, 0x00002222},

	{A5XX_RBBM_CLOCK_CNTL3_TP3, 0x00002222},

	{A5XX_RBBM_CLOCK_HYST_TP0, 0x77777777},

	{A5XX_RBBM_CLOCK_HYST_TP1, 0x77777777},

	{A5XX_RBBM_CLOCK_HYST_TP2, 0x77777777},

	{A5XX_RBBM_CLOCK_HYST_TP3, 0x77777777},

	{A5XX_RBBM_CLOCK_HYST2_TP0, 0x77777777},

	{A5XX_RBBM_CLOCK_HYST2_TP1, 0x77777777},

	{A5XX_RBBM_CLOCK_HYST2_TP2, 0x77777777},

	{A5XX_RBBM_CLOCK_HYST2_TP3, 0x77777777},

	{A5XX_RBBM_CLOCK_HYST3_TP0, 0x00007777},

	{A5XX_RBBM_CLOCK_HYST3_TP1, 0x00007777},

	{A5XX_RBBM_CLOCK_HYST3_TP2, 0x00007777},

	{A5XX_RBBM_CLOCK_HYST3_TP3, 0x00007777},

	{A5XX_RBBM_CLOCK_DELAY_TP0, 0x11111111},

	{A5XX_RBBM_CLOCK_DELAY_TP1, 0x11111111},

	{A5XX_RBBM_CLOCK_DELAY_TP2, 0x11111111},

	{A5XX_RBBM_CLOCK_DELAY_TP3, 0x11111111},

	{A5XX_RBBM_CLOCK_DELAY2_TP0, 0x11111111},

	{A5XX_RBBM_CLOCK_DELAY2_TP1, 0x11111111},

	{A5XX_RBBM_CLOCK_DELAY2_TP2, 0x11111111},

	{A5XX_RBBM_CLOCK_DELAY2_TP3, 0x11111111},

	{A5XX_RBBM_CLOCK_DELAY3_TP0, 0x00001111},

	{A5XX_RBBM_CLOCK_DELAY3_TP1, 0x00001111},

	{A5XX_RBBM_CLOCK_DELAY3_TP2, 0x00001111},

	{A5XX_RBBM_CLOCK_DELAY3_TP3, 0x00001111},

	{A5XX_RBBM_CLOCK_CNTL_UCHE, 0x22222222},

	{A5XX_RBBM_CLOCK_CNTL2_UCHE, 0x22222222},

	{A5XX_RBBM_CLOCK_CNTL3_UCHE, 0x22222222},

	{A5XX_RBBM_CLOCK_CNTL4_UCHE, 0x00222222},

	{A5XX_RBBM_CLOCK_HYST_UCHE, 0x00444444},

	{A5XX_RBBM_CLOCK_DELAY_UCHE, 0x00000002},

	{A5XX_RBBM_CLOCK_CNTL_RB0, 0x22222222},

	{A5XX_RBBM_CLOCK_CNTL_RB1, 0x22222222},

	{A5XX_RBBM_CLOCK_CNTL_RB2, 0x22222222},

	{A5XX_RBBM_CLOCK_CNTL_RB3, 0x22222222},

	{A5XX_RBBM_CLOCK_CNTL2_RB0, 0x00222222},

	{A5XX_RBBM_CLOCK_CNTL2_RB1, 0x00222222},

	{A5XX_RBBM_CLOCK_CNTL2_RB2, 0x00222222},

	{A5XX_RBBM_CLOCK_CNTL2_RB3, 0x00222222},

	{A5XX_RBBM_CLOCK_CNTL_CCU0, 0x00022220},

	{A5XX_RBBM_CLOCK_CNTL_CCU1, 0x00022220},

	{A5XX_RBBM_CLOCK_CNTL_CCU2, 0x00022220},

	{A5XX_RBBM_CLOCK_CNTL_CCU3, 0x00022220},

	{A5XX_RBBM_CLOCK_CNTL_RAC, 0x05522222},

	{A5XX_RBBM_CLOCK_CNTL2_RAC, 0x00505555},

	{A5XX_RBBM_CLOCK_HYST_RB_CCU0, 0x04040404},

	{A5XX_RBBM_CLOCK_HYST_RB_CCU1, 0x04040404},

	{A5XX_RBBM_CLOCK_HYST_RB_CCU2, 0x04040404},

	{A5XX_RBBM_CLOCK_HYST_RB_CCU3, 0x04040404},

	{A5XX_RBBM_CLOCK_HYST_RAC, 0x07444044},

	{A5XX_RBBM_CLOCK_DELAY_RB_CCU_L1_0, 0x00000002},

	{A5XX_RBBM_CLOCK_DELAY_RB_CCU_L1_1, 0x00000002},

	{A5XX_RBBM_CLOCK_DELAY_RB_CCU_L1_2, 0x00000002},

	{A5XX_RBBM_CLOCK_DELAY_RB_CCU_L1_3, 0x00000002},

	{A5XX_RBBM_CLOCK_DELAY_RAC, 0x00010011},

	{A5XX_RBBM_CLOCK_CNTL_TSE_RAS_RBBM, 0x04222222},

	{A5XX_RBBM_CLOCK_MODE_GPC, 0x02222222},

	{A5XX_RBBM_CLOCK_MODE_VFD, 0x00002222},

	{A5XX_RBBM_CLOCK_HYST_TSE_RAS_RBBM, 0x00000000},

	{A5XX_RBBM_CLOCK_HYST_GPC, 0x04104004},

	{A5XX_RBBM_CLOCK_HYST_VFD, 0x00000000},

	{A5XX_RBBM_CLOCK_DELAY_HLSQ, 0x00000000},

	{A5XX_RBBM_CLOCK_DELAY_TSE_RAS_RBBM, 0x00004000},

	{A5XX_RBBM_CLOCK_DELAY_GPC, 0x00000200},

	{A5XX_RBBM_CLOCK_DELAY_VFD, 0x00002222}

};





static const struct kgsl_hwcg_reg a540_hwcg_regs[] = {

	{A5XX_RBBM_CLOCK_CNTL_SP0, 0x02222222},

	{A5XX_RBBM_CLOCK_CNTL_SP1, 0x02222222},

	{A5XX_RBBM_CLOCK_CNTL_SP2, 0x02222222},

	{A5XX_RBBM_CLOCK_CNTL_SP3, 0x02222222},

	{A5XX_RBBM_CLOCK_CNTL2_SP0, 0x02222220},

	{A5XX_RBBM_CLOCK_CNTL2_SP1, 0x02222220},

	{A5XX_RBBM_CLOCK_CNTL2_SP2, 0x02222220},

	{A5XX_RBBM_CLOCK_CNTL2_SP3, 0x02222220},

	{A5XX_RBBM_CLOCK_HYST_SP0, 0x0000F3CF},

	{A5XX_RBBM_CLOCK_HYST_SP1, 0x0000F3CF},

	{A5XX_RBBM_CLOCK_HYST_SP2, 0x0000F3CF},

	{A5XX_RBBM_CLOCK_HYST_SP3, 0x0000F3CF},

	{A5XX_RBBM_CLOCK_DELAY_SP0, 0x00000080},

	{A5XX_RBBM_CLOCK_DELAY_SP1, 0x00000080},

	{A5XX_RBBM_CLOCK_DELAY_SP2, 0x00000080},

	{A5XX_RBBM_CLOCK_DELAY_SP3, 0x00000080},

	{A5XX_RBBM_CLOCK_CNTL_TP0, 0x22222222},

	{A5XX_RBBM_CLOCK_CNTL_TP1, 0x22222222},

	{A5XX_RBBM_CLOCK_CNTL_TP2, 0x22222222},

	{A5XX_RBBM_CLOCK_CNTL_TP3, 0x22222222},

	{A5XX_RBBM_CLOCK_CNTL2_TP0, 0x22222222},

	{A5XX_RBBM_CLOCK_CNTL2_TP1, 0x22222222},

	{A5XX_RBBM_CLOCK_CNTL2_TP2, 0x22222222},

	{A5XX_RBBM_CLOCK_CNTL2_TP3, 0x22222222},

	{A5XX_RBBM_CLOCK_CNTL3_TP0, 0x00002222},

	{A5XX_RBBM_CLOCK_CNTL3_TP1, 0x00002222},

	{A5XX_RBBM_CLOCK_CNTL3_TP2, 0x00002222},

	{A5XX_RBBM_CLOCK_CNTL3_TP3, 0x00002222},

	{A5XX_RBBM_CLOCK_HYST_TP0, 0x77777777},

	{A5XX_RBBM_CLOCK_HYST_TP1, 0x77777777},

	{A5XX_RBBM_CLOCK_HYST_TP2, 0x77777777},

	{A5XX_RBBM_CLOCK_HYST_TP3, 0x77777777},

	{A5XX_RBBM_CLOCK_HYST2_TP0, 0x77777777},

	{A5XX_RBBM_CLOCK_HYST2_TP1, 0x77777777},

	{A5XX_RBBM_CLOCK_HYST2_TP2, 0x77777777},

	{A5XX_RBBM_CLOCK_HYST2_TP3, 0x77777777},

	{A5XX_RBBM_CLOCK_HYST3_TP0, 0x00007777},

	{A5XX_RBBM_CLOCK_HYST3_TP1, 0x00007777},

	{A5XX_RBBM_CLOCK_HYST3_TP2, 0x00007777},

	{A5XX_RBBM_CLOCK_HYST3_TP3, 0x00007777},

	{A5XX_RBBM_CLOCK_DELAY_TP0, 0x11111111},

	{A5XX_RBBM_CLOCK_DELAY_TP1, 0x11111111},

	{A5XX_RBBM_CLOCK_DELAY_TP2, 0x11111111},

	{A5XX_RBBM_CLOCK_DELAY_TP3, 0x11111111},

	{A5XX_RBBM_CLOCK_DELAY2_TP0, 0x11111111},

	{A5XX_RBBM_CLOCK_DELAY2_TP1, 0x11111111},

	{A5XX_RBBM_CLOCK_DELAY2_TP2, 0x11111111},

	{A5XX_RBBM_CLOCK_DELAY2_TP3, 0x11111111},

	{A5XX_RBBM_CLOCK_DELAY3_TP0, 0x00001111},

	{A5XX_RBBM_CLOCK_DELAY3_TP1, 0x00001111},

	{A5XX_RBBM_CLOCK_DELAY3_TP2, 0x00001111},

	{A5XX_RBBM_CLOCK_DELAY3_TP3, 0x00001111},

	{A5XX_RBBM_CLOCK_CNTL_UCHE, 0x22222222},

	{A5XX_RBBM_CLOCK_CNTL2_UCHE, 0x22222222},

	{A5XX_RBBM_CLOCK_CNTL3_UCHE, 0x22222222},

	{A5XX_RBBM_CLOCK_CNTL4_UCHE, 0x00222222},

	{A5XX_RBBM_CLOCK_HYST_UCHE, 0x00444444},

	{A5XX_RBBM_CLOCK_DELAY_UCHE, 0x00000002},

	{A5XX_RBBM_CLOCK_CNTL_RB0, 0x22222222},

	{A5XX_RBBM_CLOCK_CNTL_RB1, 0x22222222},

	{A5XX_RBBM_CLOCK_CNTL_RB2, 0x22222222},

	{A5XX_RBBM_CLOCK_CNTL_RB3, 0x22222222},

	{A5XX_RBBM_CLOCK_CNTL2_RB0, 0x00222222},

	{A5XX_RBBM_CLOCK_CNTL2_RB1, 0x00222222},

	{A5XX_RBBM_CLOCK_CNTL2_RB2, 0x00222222},

	{A5XX_RBBM_CLOCK_CNTL2_RB3, 0x00222222},

	{A5XX_RBBM_CLOCK_CNTL_CCU0, 0x00022220},

	{A5XX_RBBM_CLOCK_CNTL_CCU1, 0x00022220},

	{A5XX_RBBM_CLOCK_CNTL_CCU2, 0x00022220},

	{A5XX_RBBM_CLOCK_CNTL_CCU3, 0x00022220},

	{A5XX_RBBM_CLOCK_CNTL_RAC, 0x05522222},

	{A5XX_RBBM_CLOCK_CNTL2_RAC, 0x00505555},

	{A5XX_RBBM_CLOCK_HYST_RB_CCU0, 0x04040404},

	{A5XX_RBBM_CLOCK_HYST_RB_CCU1, 0x04040404},

	{A5XX_RBBM_CLOCK_HYST_RB_CCU2, 0x04040404},

	{A5XX_RBBM_CLOCK_HYST_RB_CCU3, 0x04040404},

	{A5XX_RBBM_CLOCK_HYST_RAC, 0x07444044},

	{A5XX_RBBM_CLOCK_DELAY_RB_CCU_L1_0, 0x00000002},

	{A5XX_RBBM_CLOCK_DELAY_RB_CCU_L1_1, 0x00000002},

	{A5XX_RBBM_CLOCK_DELAY_RB_CCU_L1_2, 0x00000002},

	{A5XX_RBBM_CLOCK_DELAY_RB_CCU_L1_3, 0x00000002},

	{A5XX_RBBM_CLOCK_DELAY_RAC, 0x00010011},

	{A5XX_RBBM_CLOCK_CNTL_TSE_RAS_RBBM, 0x04222222},

	{A5XX_RBBM_CLOCK_MODE_GPC, 0x02222222},

	{A5XX_RBBM_CLOCK_MODE_VFD, 0x00002222},

	{A5XX_RBBM_CLOCK_HYST_TSE_RAS_RBBM, 0x00000000},

	{A5XX_RBBM_CLOCK_HYST_GPC, 0x04104004},

	{A5XX_RBBM_CLOCK_HYST_VFD, 0x00000000},

	{A5XX_RBBM_CLOCK_DELAY_HLSQ, 0x00000000},

	{A5XX_RBBM_CLOCK_DELAY_TSE_RAS_RBBM, 0x00004000},

	{A5XX_RBBM_CLOCK_DELAY_GPC, 0x00000200},

	{A5XX_RBBM_CLOCK_DELAY_VFD, 0x00002222},

	{A5XX_RBBM_CLOCK_HYST_GPMU, 0x00000222},

	{A5XX_RBBM_CLOCK_DELAY_GPMU, 0x00000770},

	{A5XX_RBBM_CLOCK_HYST_GPMU, 0x00000004}

};



static const struct kgsl_hwcg_reg a512_hwcg_regs[] = {

	{A5XX_RBBM_CLOCK_CNTL_SP0, 0x02222222},

	{A5XX_RBBM_CLOCK_CNTL_SP1, 0x02222222},

	{A5XX_RBBM_CLOCK_CNTL2_SP0, 0x02222220},

	{A5XX_RBBM_CLOCK_CNTL2_SP1, 0x02222220},

	{A5XX_RBBM_CLOCK_HYST_SP0, 0x0000F3CF},

	{A5XX_RBBM_CLOCK_HYST_SP1, 0x0000F3CF},

	{A5XX_RBBM_CLOCK_DELAY_SP0, 0x00000080},

	{A5XX_RBBM_CLOCK_DELAY_SP1, 0x00000080},

	{A5XX_RBBM_CLOCK_CNTL_TP0, 0x22222222},

	{A5XX_RBBM_CLOCK_CNTL_TP1, 0x22222222},

	{A5XX_RBBM_CLOCK_CNTL2_TP0, 0x22222222},

	{A5XX_RBBM_CLOCK_CNTL2_TP1, 0x22222222},

	{A5XX_RBBM_CLOCK_CNTL3_TP0, 0x00002222},

	{A5XX_RBBM_CLOCK_CNTL3_TP1, 0x00002222},

	{A5XX_RBBM_CLOCK_HYST_TP0, 0x77777777},

	{A5XX_RBBM_CLOCK_HYST_TP1, 0x77777777},

	{A5XX_RBBM_CLOCK_HYST2_TP0, 0x77777777},

	{A5XX_RBBM_CLOCK_HYST2_TP1, 0x77777777},

	{A5XX_RBBM_CLOCK_HYST3_TP0, 0x00007777},

	{A5XX_RBBM_CLOCK_HYST3_TP1, 0x00007777},

	{A5XX_RBBM_CLOCK_DELAY_TP0, 0x11111111},

	{A5XX_RBBM_CLOCK_DELAY_TP1, 0x11111111},

	{A5XX_RBBM_CLOCK_DELAY2_TP0, 0x11111111},

	{A5XX_RBBM_CLOCK_DELAY2_TP1, 0x11111111},

	{A5XX_RBBM_CLOCK_DELAY3_TP0, 0x00001111},

	{A5XX_RBBM_CLOCK_DELAY3_TP1, 0x00001111},

	{A5XX_RBBM_CLOCK_CNTL_UCHE, 0x22222222},

	{A5XX_RBBM_CLOCK_CNTL2_UCHE, 0x22222222},

	{A5XX_RBBM_CLOCK_CNTL3_UCHE, 0x22222222},

	{A5XX_RBBM_CLOCK_CNTL4_UCHE, 0x00222222},

	{A5XX_RBBM_CLOCK_HYST_UCHE, 0x00444444},

	{A5XX_RBBM_CLOCK_DELAY_UCHE, 0x00000002},

	{A5XX_RBBM_CLOCK_CNTL_RB0, 0x22222222},

	{A5XX_RBBM_CLOCK_CNTL_RB1, 0x22222222},

	{A5XX_RBBM_CLOCK_CNTL2_RB0, 0x00222222},

	{A5XX_RBBM_CLOCK_CNTL2_RB1, 0x00222222},

	{A5XX_RBBM_CLOCK_CNTL_CCU0, 0x00022220},

	{A5XX_RBBM_CLOCK_CNTL_CCU1, 0x00022220},

	{A5XX_RBBM_CLOCK_CNTL_RAC, 0x05522222},

	{A5XX_RBBM_CLOCK_CNTL2_RAC, 0x00505555},

	{A5XX_RBBM_CLOCK_HYST_RB_CCU0, 0x04040404},

	{A5XX_RBBM_CLOCK_HYST_RB_CCU1, 0x04040404},

	{A5XX_RBBM_CLOCK_HYST_RAC, 0x07444044},

	{A5XX_RBBM_CLOCK_DELAY_RB_CCU_L1_0, 0x00000002},

	{A5XX_RBBM_CLOCK_DELAY_RB_CCU_L1_1, 0x00000002},

	{A5XX_RBBM_CLOCK_DELAY_RAC, 0x00010011},

	{A5XX_RBBM_CLOCK_CNTL_TSE_RAS_RBBM, 0x04222222},

	{A5XX_RBBM_CLOCK_MODE_GPC, 0x02222222},

	{A5XX_RBBM_CLOCK_MODE_VFD, 0x00002222},

	{A5XX_RBBM_CLOCK_HYST_TSE_RAS_RBBM, 0x00000000},

	{A5XX_RBBM_CLOCK_HYST_GPC, 0x04104004},

	{A5XX_RBBM_CLOCK_HYST_VFD, 0x00000000},

	{A5XX_RBBM_CLOCK_DELAY_HLSQ, 0x00000000},

	{A5XX_RBBM_CLOCK_DELAY_TSE_RAS_RBBM, 0x00004000},

	{A5XX_RBBM_CLOCK_DELAY_GPC, 0x00000200},

	{A5XX_RBBM_CLOCK_DELAY_VFD, 0x00002222},

};



static const struct {

	int (*devfunc)(struct adreno_device *adreno_dev);

	const struct kgsl_hwcg_reg *regs;

	unsigned int count;

} a5xx_hwcg_registers[] = {

	{ adreno_is_a540, a540_hwcg_regs, ARRAY_SIZE(a540_hwcg_regs) },

	{ adreno_is_a530, a530_hwcg_regs, ARRAY_SIZE(a530_hwcg_regs) },

	{ adreno_is_a512, a512_hwcg_regs, ARRAY_SIZE(a512_hwcg_regs) },

	{ adreno_is_a510, a510_hwcg_regs, ARRAY_SIZE(a510_hwcg_regs) },

	{ adreno_is_a505, a50x_hwcg_regs, ARRAY_SIZE(a50x_hwcg_regs) },

	{ adreno_is_a506, a50x_hwcg_regs, ARRAY_SIZE(a50x_hwcg_regs) },

	{ adreno_is_a508, a50x_hwcg_regs, ARRAY_SIZE(a50x_hwcg_regs) },

};



void a5xx_hwcg_set(struct adreno_device *adreno_dev, bool on)

{

	struct kgsl_device *device = KGSL_DEVICE(adreno_dev);

	const struct kgsl_hwcg_reg *regs;

	int i, j;

	const struct adreno_a5xx_core *a5xx_core = to_a5xx_core(adreno_dev);

	int i;



	if (!test_bit(ADRENO_HWCG_CTRL, &adreno_dev->pwrctrl_flag))

		return;



	for (i = 0; i < ARRAY_SIZE(a5xx_hwcg_registers); i++) {

		if (a5xx_hwcg_registers[i].devfunc(adreno_dev))

			break;

	}



	if (i == ARRAY_SIZE(a5xx_hwcg_registers))

		return;



	regs = a5xx_hwcg_registers[i].regs;



	for (j = 0; j < a5xx_hwcg_registers[i].count; j++)

		kgsl_regwrite(device, regs[j].off, on ? regs[j].val : 0);

	for (i = 0; i < a5xx_core->hwcg_count; i++)

		kgsl_regwrite(device, a5xx_core->hwcg[i].offset,

			on ? a5xx_core->hwcg[i].value : 0);



	/* enable top level HWCG */

	kgsl_regwrite(device, A5XX_RBBM_CLOCK_CNTL, on ? 0xAAA8AA00 : 0);

drivers/gpu/msm/adreno_a5xx.h

+4 −0
Original line number Diff line number Diff line
@@ -28,6 +28,10 @@ struct adreno_a5xx_core { 
	const char *regfw_name;

	/** @zap_name: Name of the CPZ zap file */

	const char *zap_name;

	/** @hwcg: List of registers and values to write for HWCG */

	const struct adreno_reglist *hwcg;

	/** @hwcg_count: Number of registers in @hwcg */

	u32 hwcg_count;

};



#define A5XX_IRQ_FLAGS \

drivers/gpu/msm/adreno_a6xx.c

+5 −411

File changed.

Preview size limit exceeded, changes collapsed.