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Commit 9f0d1ff3 authored by Jordan Crouse's avatar Jordan Crouse
Browse files

msm: kgsl: Refactor the GPU target list 



Move the list of GPU targets from a static array to a set of structs. This
allows us to create target specific structures which are more flexible and
allows us to expand the size and scope of the GPU description for each
target family.

Change-Id: Ic0dedbade9e69bb4c4148dc0e826171a5f558d11
Signed-off-by: default avatarJordan Crouse <jcrouse@codeaurora.org>
parent 7aa1631b

drivers/gpu/msm/adreno-gpulist.h

+265 −314
Original line number Diff line number Diff line
@@ -5,462 +5,413 @@ 


#define ANY_ID (~0)



static const struct adreno_gpu_core adreno_gpulist[] = {

	{

		.gpurev = ADRENO_REV_A306,

		.core = 3,

		.major = 0,

		.minor = 6,

		.patchid = 0x00,

#define DEFINE_ADRENO_REV(_rev, _core, _major, _minor, _patchid) \

	.gpurev = _rev, .core = _core, .major = _major, .minor = _minor, \

	.patchid = _patchid



#define DEFINE_DEPRECATED_CORE(_name, _rev, _core, _major, _minor, _patchid) \

static const struct adreno_gpu_core adreno_gpu_core_##_name = { \

	DEFINE_ADRENO_REV(_rev, _core, _major, _minor, _patchid), \

	.features = ADRENO_DEPRECATED, \

}



static const struct adreno_a3xx_core adreno_gpu_core_a306 = {

	.base = {

		DEFINE_ADRENO_REV(ADRENO_REV_A306, 3, 0, 6, 0),

		.features = ADRENO_SOFT_FAULT_DETECT,

		.pm4fw_name = "a300_pm4.fw",

		.pfpfw_name = "a300_pfp.fw",

		.gpudev = &adreno_a3xx_gpudev,

		.gmem_base = 0,

		.gmem_size = SZ_128K,

		.busy_mask = 0x7FFFFFFE,

		.busy_mask = 0x7ffffffe,

	},

	{

		.gpurev = ADRENO_REV_A306A,

		.core = 3,

		.major = 0,

		.minor = 6,

		.patchid = 0x20,

		.features = ADRENO_SOFT_FAULT_DETECT,

	.pm4fw_name = "a300_pm4.fw",

	.pfpfw_name = "a300_pfp.fw",

};



static const struct adreno_a3xx_core adreno_gpu_core_a306a = {

	.base = {

		DEFINE_ADRENO_REV(ADRENO_REV_A306A, 3, 0, 6, 0x20),

		.features = ADRENO_SOFT_FAULT_DETECT,

		.gpudev = &adreno_a3xx_gpudev,

		.gmem_base = 0,

		.gmem_size = SZ_128K,

		.busy_mask = 0x7FFFFFFE,

		.busy_mask = 0x7ffffffe,

	},

	{

		.gpurev = ADRENO_REV_A304,

		.core = 3,

		.major = 0,

		.minor = 4,

		.patchid = 0x00,

		.features = ADRENO_SOFT_FAULT_DETECT,

	.pm4fw_name = "a300_pm4.fw",

	.pfpfw_name = "a300_pfp.fw",

};



static const struct adreno_a3xx_core adreno_gpu_core_a304 = {

	.base = {

		DEFINE_ADRENO_REV(ADRENO_REV_A304, 3, 0, 4, 0),

		.features = ADRENO_SOFT_FAULT_DETECT,

		.gpudev = &adreno_a3xx_gpudev,

		.gmem_base = 0,

		.gmem_size = (SZ_64K + SZ_32K),

		.busy_mask = 0x7FFFFFFE,

	},

	{

		.gpurev = ADRENO_REV_A405,

		.core = 4,

		.major = 0,

		.minor = 5,

		.patchid = ANY_ID,

		.features = ADRENO_DEPRECATED,

	},

	{

		.gpurev = ADRENO_REV_A420,

		.core = 4,

		.major = 2,

		.minor = 0,

		.patchid = ANY_ID,

		.features = ADRENO_DEPRECATED,

	},

	{

		.gpurev = ADRENO_REV_A430,

		.core = 4,

		.major = 3,

		.minor = 0,

		.patchid = ANY_ID,

		.features = ADRENO_DEPRECATED,

	},

	{

		.gpurev = ADRENO_REV_A418,

		.core = 4,

		.major = 1,

		.minor = 8,

		.patchid = ANY_ID,

		.features = ADRENO_DEPRECATED,

	},

	{

		.gpurev = ADRENO_REV_A530,

		.core = 5,

		.major = 3,

		.minor = 0,

		.patchid = 0,

		.features = ADRENO_DEPRECATED,

		.busy_mask = 0x7ffffffe,

	},

	{

		.gpurev = ADRENO_REV_A530,

		.core = 5,

		.major = 3,

		.minor = 0,

		.patchid = 1,

	.pm4fw_name = "a300_pm4.fw",

	.pfpfw_name = "a300_pfp.fw",

};



DEFINE_DEPRECATED_CORE(a405, ADRENO_REV_A405, 4, 0, 5, ANY_ID);

DEFINE_DEPRECATED_CORE(a418, ADRENO_REV_A418, 4, 1, 8, ANY_ID);

DEFINE_DEPRECATED_CORE(a420, ADRENO_REV_A420, 4, 2, 0, ANY_ID);

DEFINE_DEPRECATED_CORE(a430, ADRENO_REV_A430, 4, 3, 0, ANY_ID);

DEFINE_DEPRECATED_CORE(a530v1, ADRENO_REV_A530, 5, 3, 0, 0);



static const struct adreno_a5xx_core adreno_gpu_core_a530v2 = {

	.base = {

		DEFINE_ADRENO_REV(ADRENO_REV_A530, 5, 3, 0, 1),

		.features = ADRENO_GPMU | ADRENO_SPTP_PC | ADRENO_LM |

			ADRENO_PREEMPTION | ADRENO_64BIT |

			ADRENO_CONTENT_PROTECTION,

		.pm4fw_name = "a530_pm4.fw",

		.pfpfw_name = "a530_pfp.fw",

		.zap_name = "a530_zap",

		.gpudev = &adreno_a5xx_gpudev,

		.gmem_base = 0x100000,

		.gmem_size = SZ_1M,

		.num_protected_regs = 0x20,

		.gpmufw_name = "a530_gpmu.fw2",

		.gpmu_major = 1,

		.gpmu_minor = 0,

		.busy_mask = 0xFFFFFFFE,

		.lm_major = 3,

		.lm_minor = 0,

		.busy_mask = 0xfffffffe,

	},

	.gpmu_tsens = 0x00060007,

	.max_power = 5448,

	.pm4fw_name = "a530_pm4.fw",

	.pfpfw_name = "a530_pfp.fw",

	.gpmufw_name = "a530_gpmu.fw2",

	.regfw_name = "a530v2_seq.fw2",

	},

	{

		.gpurev = ADRENO_REV_A530,

		.core = 5,

		.major = 3,

		.minor = 0,

		.patchid = ANY_ID,

	.zap_name = "a530_zap",

};



static const struct adreno_a5xx_core adreno_gpu_core_a530v3 = {

	.base = {

		DEFINE_ADRENO_REV(ADRENO_REV_A530, 5, 3, 0, ANY_ID),

		.features = ADRENO_GPMU | ADRENO_SPTP_PC | ADRENO_LM |

			ADRENO_PREEMPTION | ADRENO_64BIT |

			ADRENO_CONTENT_PROTECTION,

		.pm4fw_name = "a530_pm4.fw",

		.pfpfw_name = "a530_pfp.fw",

		.zap_name = "a530_zap",

		.gpudev = &adreno_a5xx_gpudev,

		.gmem_base = 0x100000,

		.gmem_size = SZ_1M,

		.num_protected_regs = 0x20,

		.gpmufw_name = "a530v3_gpmu.fw2",

		.gpmu_major = 1,

		.gpmu_minor = 0,

		.busy_mask = 0xFFFFFFFE,

		.lm_major = 1,

		.lm_minor = 0,

		.busy_mask = 0xfffffffe,

	},

	.gpmu_tsens = 0x00060007,

	.max_power = 5448,

		.regfw_name = "a530v3_seq.fw2",

	},

	{

		.gpurev = ADRENO_REV_A505,

		.core = 5,

		.major = 0,

		.minor = 5,

		.patchid = ANY_ID,

		.features = ADRENO_PREEMPTION | ADRENO_64BIT,

	.pm4fw_name = "a530_pm4.fw",

	.pfpfw_name = "a530_pfp.fw",

	.gpmufw_name = "a530v3_gpmu.fw2",

	.regfw_name = "a530v3_seq.fw2",

	.zap_name = "a530_zap",

};



static const struct adreno_a5xx_core adreno_gpu_core_a505 = {

	.base = {

		DEFINE_ADRENO_REV(ADRENO_REV_A505, 5, 0, 5, ANY_ID),

		.features = ADRENO_PREEMPTION | ADRENO_64BIT,

		.gpudev = &adreno_a5xx_gpudev,

		.gmem_base = 0x100000,

		.gmem_size = (SZ_128K + SZ_8K),

		.num_protected_regs = 0x20,

		.busy_mask = 0xFFFFFFFE,

		.busy_mask = 0xfffffffe,

	},

	{

		.gpurev = ADRENO_REV_A506,

		.core = 5,

		.major = 0,

		.minor = 6,

		.patchid = ANY_ID,

		.features = ADRENO_PREEMPTION | ADRENO_64BIT |

			ADRENO_CONTENT_PROTECTION | ADRENO_CPZ_RETENTION,

	.pm4fw_name = "a530_pm4.fw",

	.pfpfw_name = "a530_pfp.fw",

		.zap_name = "a506_zap",

};



static const struct adreno_a5xx_core adreno_gpu_core_a506 = {

	.base = {

		DEFINE_ADRENO_REV(ADRENO_REV_A506, 5, 0, 6, ANY_ID),

		.features = ADRENO_PREEMPTION | ADRENO_64BIT |

			ADRENO_CONTENT_PROTECTION | ADRENO_CPZ_RETENTION,

		.gpudev = &adreno_a5xx_gpudev,

		.gmem_base = 0x100000,

		.gmem_size = (SZ_128K + SZ_8K),

		.num_protected_regs = 0x20,

		.busy_mask = 0xFFFFFFFE,

		.busy_mask = 0xfffffffe,

	},

	{

		.gpurev = ADRENO_REV_A510,

		.core = 5,

		.major = 1,

		.minor = 0,

		.patchid = ANY_ID,

	.pm4fw_name = "a530_pm4.fw",

	.pfpfw_name = "a530_pfp.fw",

	.zap_name = "a506_zap",

};



static const struct adreno_a5xx_core adreno_gpu_core_a510 = {

	.base = {

		DEFINE_ADRENO_REV(ADRENO_REV_A510, 5, 1, 0, ANY_ID),

		.gpudev = &adreno_a5xx_gpudev,

		.gmem_base = 0x100000,

		.gmem_size = SZ_256K,

		.num_protected_regs = 0x20,

		.busy_mask = 0xFFFFFFFE,

	},

	{

		.gpurev = ADRENO_REV_A540,

		.core = 5,

		.major = 4,

		.minor = 0,

		.patchid = 0,

		.features = ADRENO_DEPRECATED,

		.busy_mask = 0xfffffffe,

	},

	{

		.gpurev = ADRENO_REV_A540,

		.core = 5,

		.major = 4,

		.minor = 0,

		.patchid = ANY_ID,

	.pm4fw_name = "a530_pm4.fw",

	.pfpfw_name = "a530_pfp.fw",

};



DEFINE_DEPRECATED_CORE(a540v1, ADRENO_REV_A540, 5, 4, 0, 0);



static const struct adreno_a5xx_core adreno_gpu_core_a540v2 = {

	.base = {

		DEFINE_ADRENO_REV(ADRENO_REV_A540, 5, 4, 0, ANY_ID),

		.features = ADRENO_PREEMPTION | ADRENO_64BIT |

			ADRENO_CONTENT_PROTECTION |

			ADRENO_GPMU | ADRENO_SPTP_PC,

		.pm4fw_name = "a530_pm4.fw",

		.pfpfw_name = "a530_pfp.fw",

		.zap_name = "a540_zap",

		.gpudev = &adreno_a5xx_gpudev,

		.gmem_base = 0x100000,

		.gmem_size = SZ_1M,

		.num_protected_regs = 0x20,

		.busy_mask = 0xFFFFFFFE,

		.gpmufw_name = "a540_gpmu.fw2",

		.gpmu_major = 3,

		.gpmu_minor = 0,

		.gpmu_tsens = 0x000C000D,

		.max_power = 5448,

		.busy_mask = 0xfffffffe,

	},

	{

		.gpurev = ADRENO_REV_A512,

		.core = 5,

		.major = 1,

		.minor = 2,

		.patchid = ANY_ID,

		.features = ADRENO_PREEMPTION | ADRENO_64BIT |

			ADRENO_CONTENT_PROTECTION | ADRENO_CPZ_RETENTION,

	.gpmu_tsens = 0x000c000d,

	.max_power = 5448,

	.pm4fw_name = "a530_pm4.fw",

	.pfpfw_name = "a530_pfp.fw",

		.zap_name = "a512_zap",

	.gpmufw_name = "a540_gpmu.fw2",

	.zap_name = "a540_zap",

};



static const struct adreno_a5xx_core adreno_gpu_core_a512 = {

	.base = {

		DEFINE_ADRENO_REV(ADRENO_REV_A512, 5, 1, 2, ANY_ID),

		.features = ADRENO_PREEMPTION | ADRENO_64BIT |

			ADRENO_CONTENT_PROTECTION | ADRENO_CPZ_RETENTION,

		.gpudev = &adreno_a5xx_gpudev,

		.gmem_base = 0x100000,

		.gmem_size = (SZ_256K + SZ_16K),

		.num_protected_regs = 0x20,

		.busy_mask = 0xFFFFFFFE,

		.busy_mask = 0xfffffffe,

	},

	{

		.gpurev = ADRENO_REV_A508,

		.core = 5,

		.major = 0,

		.minor = 8,

		.patchid = ANY_ID,

		.features = ADRENO_PREEMPTION | ADRENO_64BIT |

			ADRENO_CONTENT_PROTECTION | ADRENO_CPZ_RETENTION,

	.pm4fw_name = "a530_pm4.fw",

	.pfpfw_name = "a530_pfp.fw",

		.zap_name = "a508_zap",

	.zap_name = "a512_zap",

};



static const struct adreno_a5xx_core adreno_gpu_core_a508 = {

	.base = {

		DEFINE_ADRENO_REV(ADRENO_REV_A508, 5, 0, 8, ANY_ID),

		.features = ADRENO_PREEMPTION | ADRENO_64BIT |

			ADRENO_CONTENT_PROTECTION | ADRENO_CPZ_RETENTION,

		.gpudev = &adreno_a5xx_gpudev,

		.gmem_base = 0x100000,

		.gmem_size = (SZ_128K + SZ_8K),

		.num_protected_regs = 0x20,

		.busy_mask = 0xFFFFFFFE,

		.busy_mask = 0xfffffffe,

	},

	{

		.gpurev = ADRENO_REV_A630,

		.core = 6,

		.major = 3,

		.minor = 0,

		.patchid = 0,

		.features = ADRENO_DEPRECATED,

	},

	{

		.gpurev = ADRENO_REV_A630,

		.core = 6,

		.major = 3,

		.minor = 0,

		.patchid = ANY_ID,

	.pm4fw_name = "a530_pm4.fw",

	.pfpfw_name = "a530_pfp.fw",

	.zap_name = "a508_zap",

};



DEFINE_DEPRECATED_CORE(a630v1, ADRENO_REV_A630, 6, 3, 0, 0);



static const struct adreno_a6xx_core adreno_gpu_core_a630v2 = {

	.base = {

		DEFINE_ADRENO_REV(ADRENO_REV_A630, 6, 3, 0, ANY_ID),

		.features = ADRENO_64BIT | ADRENO_RPMH | ADRENO_IFPC |

			ADRENO_GPMU | ADRENO_CONTENT_PROTECTION |

			ADRENO_IOCOHERENT | ADRENO_PREEMPTION,

		.sqefw_name = "a630_sqe.fw",

		.zap_name = "a630_zap",

		.gpudev = &adreno_a6xx_gpudev,

		.gmem_base = 0x100000,

		.gmem_size = SZ_1M,

		.num_protected_regs = 0x20,

		.busy_mask = 0xFFFFFFFE,

		.gpmufw_name = "a630_gmu.bin",

		.gpmu_major = 0x1,

		.gpmu_minor = 0x003,

		.gpmu_tsens = 0x000C000D,

		.max_power = 5448,

		.busy_mask = 0xfffffffe,

	},

	.prim_fifo_threshold = 0x0018000,

	.pdc_address_offset = 0x00030080,

	},

	{

		.gpurev = ADRENO_REV_A615,

		.core = 6,

		.major = 1,

		.minor = 5,

		.patchid = ANY_ID,

	.gmu_major = 1,

	.gmu_minor = 3,

	.sqefw_name = "a630_sqe.fw",

	.gmufw_name = "a630_gmu.bin",

	.zap_name = "a630_zap",

};



static const struct adreno_a6xx_core adreno_gpu_core_a615 = {

	.base = {

		DEFINE_ADRENO_REV(ADRENO_REV_A615, 6, 1, 5, ANY_ID),

		.features = ADRENO_64BIT | ADRENO_RPMH | ADRENO_PREEMPTION |

			ADRENO_GPMU | ADRENO_CONTENT_PROTECTION | ADRENO_IFPC |

			ADRENO_IOCOHERENT,

		.sqefw_name = "a630_sqe.fw",

		.zap_name = "a615_zap",

		.gpudev = &adreno_a6xx_gpudev,

		.gmem_base = 0x100000,

		.gmem_size = SZ_512K,

		.num_protected_regs = 0x20,

		.busy_mask = 0xFFFFFFFE,

		.gpmufw_name = "a630_gmu.bin",

		.gpmu_major = 0x1,

		.gpmu_minor = 0x003,

		.busy_mask = 0xfffffffe,

	},

	.prim_fifo_threshold = 0x0018000,

	.pdc_address_offset = 0x00030080,

	},

	{

		.gpurev = ADRENO_REV_A618,

		.core = 6,

		.major = 1,

		.minor = 8,

		.patchid = ANY_ID,

	.gmu_major = 1,

	.gmu_minor = 3,

	.sqefw_name = "a630_sqe.fw",

	.gmufw_name = "a630_gmu.bin",

	.zap_name = "a615_zap",

};



static const struct adreno_a6xx_core adreno_gpu_core_a618 = {

	.base = {

		DEFINE_ADRENO_REV(ADRENO_REV_A618, 6, 1, 8, ANY_ID),

		.features = ADRENO_64BIT | ADRENO_RPMH | ADRENO_PREEMPTION |

			ADRENO_GPMU | ADRENO_CONTENT_PROTECTION | ADRENO_IFPC |

			ADRENO_IOCOHERENT,

		.sqefw_name = "a630_sqe.fw",

		.zap_name = "a615_zap",

		.gpudev = &adreno_a6xx_gpudev,

		.gmem_base = 0x100000,

		.gmem_size = SZ_512K,

		.num_protected_regs = 0x20,

		.busy_mask = 0xFFFFFFFE,

		.gpmufw_name = "a630_gmu.bin",

		.gpmu_major = 0x1,

		.gpmu_minor = 0x007,

		.busy_mask = 0xfffffffe,

	},

	.prim_fifo_threshold = 0x0018000,

	.pdc_address_offset = 0x00030090,

	},

	{

		.gpurev = ADRENO_REV_A620,

		.core = 6,

		.major = 2,

		.minor = 0,

		.patchid = 0,

	.gmu_major = 1,

	.gmu_minor = 7,

	.sqefw_name = "a630_sqe.fw",

	.gmufw_name = "a630_gmu.bin",

	.zap_name = "a615_zap",

};



static const struct adreno_a6xx_core adreno_gpu_core_a620 = {

	.base = {

		DEFINE_ADRENO_REV(ADRENO_REV_A618, 6, 2, 0, 0),

		.features = ADRENO_64BIT | ADRENO_RPMH | ADRENO_GPMU |

			ADRENO_CONTENT_PROTECTION | ADRENO_IOCOHERENT |

			ADRENO_IFPC,

		.sqefw_name = "a650_sqe.fw",

		.zap_name = "a620_zap",

		.gpudev = &adreno_a6xx_gpudev,

		.gmem_base = 0,

		.gmem_size = SZ_512K,

		.num_protected_regs = 0x30,

		.busy_mask = 0xFFFFFFFE,

		.gpmufw_name = "a650_gmu.bin",

		.gpmu_major = 0x2,

		.gpmu_minor = 0x000,

		.gpmu_tsens = 0x000C000D,

		.max_power = 5448,

		.prim_fifo_threshold = 0x100000,

		.pdc_address_offset = 0x000300A0,

		.busy_mask = 0xfffffffe,

	},

	{

		.gpurev = ADRENO_REV_A640,

		.core = 6,

		.major = 4,

		.minor = 0,

		.patchid = ANY_ID,

	.prim_fifo_threshold = 0x0010000,

	.pdc_address_offset = 0x000300a0,

	.gmu_major = 2,

	.gmu_minor = 0,

	.sqefw_name = "a650_sqe.fw",

	.gmufw_name = "a650_gmu.bin",

	.zap_name = "a620_zap",

};



static const struct adreno_a6xx_core adreno_gpu_core_a640 = {

	.base = {

		DEFINE_ADRENO_REV(ADRENO_REV_A640, 6, 4, 0, ANY_ID),

		.features = ADRENO_64BIT | ADRENO_RPMH | ADRENO_GPMU |

			ADRENO_CONTENT_PROTECTION | ADRENO_IOCOHERENT |

			ADRENO_IFPC | ADRENO_PREEMPTION,

		.sqefw_name = "a630_sqe.fw",

		.zap_name = "a640_zap",

		.gpudev = &adreno_a6xx_gpudev,

		.gmem_base = 0x100000,

		.gmem_size = SZ_1M, //Verified 1MB

		.num_protected_regs = 0x20,

		.busy_mask = 0xFFFFFFFE,

		.gpmufw_name = "a640_gmu.bin",

		.gpmu_major = 0x2,

		.gpmu_minor = 0x000,

		.gpmu_tsens = 0x000C000D,

		.max_power = 5448,

		.busy_mask = 0xfffffffe,

	},

	.prim_fifo_threshold = 0x00200000,

	.pdc_address_offset = 0x00030090,

	},

	.gmu_major = 2,

	.gmu_minor = 0,

	.sqefw_name = "a630_sqe.fw",

	.gmufw_name = "a640_gmu.bin",

	.zap_name = "a640_zap",

};



static const struct adreno_a6xx_core adreno_gpu_core_a650 = {

	{

		.gpurev = ADRENO_REV_A650,

		.core = 6,

		.major = 5,

		.minor = 0,

		.patchid = 0,

		DEFINE_ADRENO_REV(ADRENO_REV_A650, 6, 5, 0, 0),

		.features = ADRENO_64BIT | ADRENO_RPMH | ADRENO_GPMU |

			ADRENO_IOCOHERENT | ADRENO_CONTENT_PROTECTION |

			ADRENO_IFPC,

		.sqefw_name = "a650_sqe.fw",

		.zap_name = "a650_zap",

		.gpudev = &adreno_a6xx_gpudev,

		.gmem_base = 0,

		.gmem_size = SZ_1M + SZ_128K, /* verified 1152kB */

		.num_protected_regs = 0x30,

		.busy_mask = 0xFFFFFFFE,

		.gpmufw_name = "a650_gmu.bin",

		.gpmu_major = 0x2,

		.gpmu_minor = 0x000,

		.gpmu_tsens = 0x000C000D,

		.max_power = 5448,

		.busy_mask = 0xfffffffe,

	},

	.prim_fifo_threshold = 0x00300000,

	.pdc_address_offset = 0x000300A0,

	},

	{

		.gpurev = ADRENO_REV_A680,

		.core = 6,

		.major = 8,

		.minor = 0,

		.patchid = ANY_ID,

	.gmu_major = 2,

	.gmu_minor = 0,

	.sqefw_name = "a650_sqe.fw",

	.gmufw_name = "a650_gmu.bin",

	.zap_name = "a650_zap",

};



static const struct adreno_a6xx_core adreno_gpu_core_a680 = {

	.base = {

		DEFINE_ADRENO_REV(ADRENO_REV_A680, 6, 8, 0, ANY_ID),

		.features = ADRENO_64BIT | ADRENO_RPMH | ADRENO_GPMU,

		.sqefw_name = "a630_sqe.fw",

		.zap_name = "a640_zap",

		.gpudev = &adreno_a6xx_gpudev,

		.gmem_base = 0x100000,

		.gmem_size = SZ_2M,

		.num_protected_regs = 0x20,

		.busy_mask = 0xFFFFFFFE,

		.gpmufw_name = "a640_gmu.bin",

		.gpmu_major = 0x2,

		.gpmu_minor = 0x000,

		.gpmu_tsens = 0x000C000D,

		.max_power = 5448,

		.busy_mask = 0xfffffffe,

	},

	.prim_fifo_threshold = 0x00400000,

	.pdc_address_offset = 0x00030090,

	},

	.gmu_major = 2,

	.gmu_minor = 0,

	.sqefw_name = "a630_sqe.fw",

	.gmufw_name = "a640_gmu.bin",

	.zap_name = "a640_zap",

};



static const struct adreno_a6xx_core adreno_gpu_core_a612 = {

	{

		.gpurev = ADRENO_REV_A612,

		.core = 6,

		.major = 1,

		.minor = 2,

		.patchid = ANY_ID,

		DEFINE_ADRENO_REV(ADRENO_REV_A612, 6, 1, 2, ANY_ID),

		.features = ADRENO_64BIT | ADRENO_CONTENT_PROTECTION |

			ADRENO_IOCOHERENT | ADRENO_PREEMPTION | ADRENO_GPMU |

			ADRENO_IFPC | ADRENO_PERFCTRL_RETAIN,

		.sqefw_name = "a630_sqe.fw",

		.zap_name = "a612_zap",

		.gpudev = &adreno_a6xx_gpudev,

		.gmem_base = 0x100000,

		.gmem_size = (SZ_128K + SZ_4K),

		.num_protected_regs = 0x20,

		.busy_mask = 0xFFFFFFFE,

		.gpmufw_name = "a612_rgmu.bin",

		.busy_mask = 0xfffffffe,

	},

	.prim_fifo_threshold = 0x00080000,

	.pdc_address_offset = 0x00030080,

	},

	.sqefw_name = "a630_sqe.fw",

	.gmufw_name = "a612_rgmu.bin",

	.zap_name = "a612_zap",

};



static const struct adreno_a6xx_core adreno_gpu_core_a616 = {

	{

		.gpurev = ADRENO_REV_A616,

		.core = 6,

		.major = 1,

		.minor = 6,

		.patchid = ANY_ID,

		DEFINE_ADRENO_REV(ADRENO_REV_A616, 6, 1, 6, ANY_ID),

		.features = ADRENO_64BIT | ADRENO_RPMH | ADRENO_PREEMPTION |

			ADRENO_GPMU | ADRENO_CONTENT_PROTECTION | ADRENO_IFPC |

			ADRENO_IOCOHERENT,

		.sqefw_name = "a630_sqe.fw",

		.zap_name = "a615_zap",

		.gpudev = &adreno_a6xx_gpudev,

		.gmem_base = 0x100000,

		.gmem_size = SZ_512K,

		.num_protected_regs = 0x20,

		.busy_mask = 0xFFFFFFFE,

		.gpmufw_name = "a630_gmu.bin",

		.gpmu_major = 0x1,

		.gpmu_minor = 0x003,

		.busy_mask = 0xfffffffe,

	},

	.prim_fifo_threshold = 0x0018000,

	.pdc_address_offset = 0x00030080,

	},

	.gmu_major = 1,

	.gmu_minor = 3,

	.sqefw_name = "a630_sqe.fw",

	.gmufw_name = "a630_gmu.bin",

	.zap_name = "a615_zap",

};



static const struct adreno_gpu_core *adreno_gpulist[] = {

	&adreno_gpu_core_a306.base,

	&adreno_gpu_core_a306a.base,

	&adreno_gpu_core_a304.base,

	&adreno_gpu_core_a405,		/* Deprecated */

	&adreno_gpu_core_a418,		/* Deprecated */

	&adreno_gpu_core_a420,		/* Deprecated */

	&adreno_gpu_core_a430,		/* Deprecated */

	&adreno_gpu_core_a530v1,	/* Deprecated */

	&adreno_gpu_core_a530v2.base,

	&adreno_gpu_core_a530v3.base,

	&adreno_gpu_core_a505.base,

	&adreno_gpu_core_a506.base,

	&adreno_gpu_core_a510.base,

	&adreno_gpu_core_a540v1,	/* Deprecated */

	&adreno_gpu_core_a540v2.base,

	&adreno_gpu_core_a512.base,

	&adreno_gpu_core_a508.base,

	&adreno_gpu_core_a630v1,	/* Deprecated */

	&adreno_gpu_core_a630v2.base,

	&adreno_gpu_core_a615.base,

	&adreno_gpu_core_a618.base,

	&adreno_gpu_core_a620.base,

	&adreno_gpu_core_a640.base,

	&adreno_gpu_core_a650.base,

	&adreno_gpu_core_a680.base,

	&adreno_gpu_core_a612.base,

	&adreno_gpu_core_a616.base,

};

drivers/gpu/msm/adreno.c

+9 −24
Original line number Diff line number Diff line
@@ -30,8 +30,10 @@ 
#include "adreno_pm4types.h"

#include "adreno_trace.h"



#include "a3xx_reg.h"

#include "a6xx_reg.h"

#include "adreno_a3xx.h"

#include "adreno_a5xx.h"

#include "adreno_a6xx.h"



#include "adreno_snapshot.h"



/* Include the master list of GPU cores that are supported */
@@ -684,11 +686,11 @@ static inline const struct adreno_gpu_core *_get_gpu_core(unsigned int chipid) 
	int i;



	for (i = 0; i < ARRAY_SIZE(adreno_gpulist); i++) {

		if (core == adreno_gpulist[i].core &&

		    _rev_match(major, adreno_gpulist[i].major) &&

		    _rev_match(minor, adreno_gpulist[i].minor) &&

		    _rev_match(patchid, adreno_gpulist[i].patchid))

			return &adreno_gpulist[i];

		if (core == adreno_gpulist[i]->core &&

		    _rev_match(major, adreno_gpulist[i]->major) &&

		    _rev_match(minor, adreno_gpulist[i]->minor) &&

		    _rev_match(patchid, adreno_gpulist[i]->patchid))

			return adreno_gpulist[i];

	}



	return NULL;
@@ -1629,23 +1631,6 @@ static int adreno_init(struct kgsl_device *device) 


	set_bit(ADRENO_DEVICE_INITIALIZED, &adreno_dev->priv);



	/* Use shader offset and length defined in gpudev */

	if (adreno_dev->gpucore->shader_offset &&

					adreno_dev->gpucore->shader_size) {



		if (device->shader_mem_phys || device->shader_mem_virt)

			dev_err(device->dev,

				     "Shader memory already specified in device tree\n");

		else {

			device->shader_mem_phys = device->reg_phys +

					adreno_dev->gpucore->shader_offset;

			device->shader_mem_virt = device->reg_virt +

					adreno_dev->gpucore->shader_offset;

			device->shader_mem_len =

					adreno_dev->gpucore->shader_size;

		}

	}



	/*

	 * Allocate a small chunk of memory for precise drawobj profiling for

	 * those targets that have the always on timer

drivers/gpu/msm/adreno.h

+0 −31
Original line number Diff line number Diff line
@@ -344,54 +344,23 @@ struct adreno_device_private { 
 * @minor: Match for the minor version of the GPU

 * @patchid: Match for the patch revision of the GPU

 * @features: Common adreno features supported by this core

 * @pm4fw_name: Filename for th PM4 firmware

 * @pfpfw_name: Filename for the PFP firmware

 * @zap_name: Filename for the Zap Shader ucode

 * @gpudev: Pointer to the GPU family specific functions for this core

 * @gmem_base: Base address of binning memory (GMEM/OCMEM)

 * @gmem_size: Amount of binning memory (GMEM/OCMEM) to reserve for the core

 * @shader_offset: Offset of shader from gpu reg base

 * @shader_size: Shader size

 * @num_protected_regs: number of protected registers

 * @gpmufw_name: Filename for the GPMU firmware

 * @gpmu_major: Match for the GPMU & firmware, major revision

 * @gpmu_minor: Match for the GPMU & firmware, minor revision

 * @gpmu_features: Supported features for any given GPMU version

 * @busy_mask: mask to check if GPU is busy in RBBM_STATUS

 * @lm_major: Limits Management register sequence, major revision

 * @lm_minor: LM register sequence, minor revision

 * @regfw_name: Filename for the register sequence firmware

 * @gpmu_tsens: ID for the temporature sensor used by the GPMU

 * @max_power: Max possible power draw of a core, units elephant tail hairs

 */

struct adreno_gpu_core {

	enum adreno_gpurev gpurev;

	unsigned int core, major, minor, patchid;

	unsigned long features;

	const char *pm4fw_name;

	const char *pfpfw_name;

	const char *sqefw_name;

	const char *zap_name;

	struct adreno_gpudev *gpudev;

	unsigned long gmem_base;

	size_t gmem_size;

	unsigned long shader_offset;

	unsigned int shader_size;

	unsigned int num_protected_regs;

	const char *gpmufw_name;

	unsigned int gpmu_major;

	unsigned int gpmu_minor;

	unsigned int gpmu_features;

	unsigned int busy_mask;

	unsigned int lm_major, lm_minor;

	const char *regfw_name;

	unsigned int gpmu_tsens;

	unsigned int max_power;

	unsigned int prim_fifo_threshold;

	unsigned int pdc_address_offset;

};





enum gpu_coresight_sources {

	GPU_CORESIGHT_GX = 0,

	GPU_CORESIGHT_CX = 1,

drivers/gpu/msm/adreno_a3xx.c

+5 −4
Original line number Diff line number Diff line
@@ -1394,17 +1394,18 @@ static int a3xx_microcode_read(struct adreno_device *adreno_dev) 
	struct kgsl_device *device = KGSL_DEVICE(adreno_dev);

	struct adreno_firmware *pm4_fw = ADRENO_FW(adreno_dev, ADRENO_FW_PM4);

	struct adreno_firmware *pfp_fw = ADRENO_FW(adreno_dev, ADRENO_FW_PFP);

	const struct adreno_a3xx_core *a3xx_core = to_a3xx_core(adreno_dev);



	if (pm4_fw->fwvirt == NULL) {

		int len;

		void *ptr;



		int ret = _load_firmware(device,

			adreno_dev->gpucore->pm4fw_name, &ptr, &len);

			a3xx_core->pm4fw_name, &ptr, &len);



		if (ret) {

			dev_err(device->dev,  "Failed to read pm4 ucode %s\n",

				adreno_dev->gpucore->pm4fw_name);

				a3xx_core->pm4fw_name);

			return ret;

		}
@@ -1427,10 +1428,10 @@ static int a3xx_microcode_read(struct adreno_device *adreno_dev) 
		void *ptr;



		int ret = _load_firmware(device,

			adreno_dev->gpucore->pfpfw_name, &ptr, &len);

			a3xx_core->pfpfw_name, &ptr, &len);

		if (ret) {

			dev_err(device->dev, "Failed to read pfp ucode %s\n",

					   adreno_dev->gpucore->pfpfw_name);

					   a3xx_core->pfpfw_name);

			return ret;

		}

drivers/gpu/msm/adreno_a3xx.h

+26 −0
Original line number Diff line number Diff line
@@ -6,6 +6,17 @@ 
#define __A3XX_H



#include "a3xx_reg.h"

/**

 * struct adreno_a3xx_core - a3xx specific GPU core definitions

 */

struct adreno_a3xx_core {

	/** @base: Container for the generic &struct adreno_gpu_core */

	struct adreno_gpu_core base;

	/** pm4fw_name: Name of the PM4 microcode file */

	const char *pm4fw_name;

	/** pfpfw_name: Name of the PFP microcode file */

	const char *pfpfw_name;

};



#define A3XX_IRQ_FLAGS \

	{ BIT(A3XX_INT_RBBM_GPU_IDLE), "RBBM_GPU_IDLE" }, \
@@ -33,6 +44,21 @@ 
	{ BIT(A3XX_INT_MISC_HANG_DETECT), "MISC_HANG_DETECT" }, \

	{ BIT(A3XX_INT_UCHE_OOB_ACCESS), "UCHE_OOB_ACCESS" }



/**

 * to_a3xx_core - return the a3xx specific GPU core struct

 * @adreno_dev: An Adreno GPU device handle

 *

 * Returns:

 * A pointer to the a3xx specific GPU core struct

 */

static inline const struct adreno_a3xx_core *

to_a3xx_core(struct adreno_device *adreno_dev)

{

	const struct adreno_gpu_core *core = adreno_dev->gpucore;



	return container_of(core, struct adreno_a3xx_core, base);

}



unsigned int a3xx_irq_pending(struct adreno_device *adreno_dev);



void a3xx_snapshot(struct adreno_device *adreno_dev,