Merge "disp: msm: pll: add additional dividers for CPHY support" (a9abdd90) · Commits · e / devices / android_kernel_fairphone_FP4

msm/dsi/dsi_ctrl.c

+27 −10

Original line number	Diff line number	Diff line
		@@ -880,6 +880,7 @@ static int dsi_ctrl_update_link_freqs(struct dsi_ctrl *dsi_ctrl,
		{
		int rc = 0;
		u32 num_of_lanes = 0;
		u32 bits_per_symbol = 16, num_of_symbols = 7; /* For Cphy */
		u32 bpp, frame_time_us, byte_intf_clk_div;
		u64 h_period, v_period, bit_rate, pclk_rate, bit_rate_per_lane,
		byte_clk_rate, byte_intf_clk_rate;
		@@ -910,6 +911,10 @@ static int dsi_ctrl_update_link_freqs(struct dsi_ctrl *dsi_ctrl,

		if (config->bit_clk_rate_hz_override != 0) {
		bit_rate = config->bit_clk_rate_hz_override * num_of_lanes;
		if (host_cfg->phy_type == DSI_PHY_TYPE_CPHY) {
		bit_rate *= bits_per_symbol;
		do_div(bit_rate, num_of_symbols);
		}
		} else if (config->panel_mode == DSI_OP_CMD_MODE) {
		/* Calculate the bit rate needed to match dsi transfer time */
		bit_rate = min_dsi_clk_hz * frame_time_us;
		@@ -921,16 +926,29 @@ static int dsi_ctrl_update_link_freqs(struct dsi_ctrl *dsi_ctrl,
		bit_rate = h_period * v_period * timing->refresh_rate * bpp;
		}

		bit_rate_per_lane = bit_rate;
		do_div(bit_rate_per_lane, num_of_lanes);

		pclk_rate = bit_rate;
		do_div(pclk_rate, bpp);
		if (host_cfg->phy_type == DSI_PHY_TYPE_DPHY) {
		bit_rate_per_lane = bit_rate;
		do_div(bit_rate_per_lane, num_of_lanes);
		byte_clk_rate = bit_rate_per_lane;
		do_div(byte_clk_rate, 8);
		byte_intf_clk_rate = byte_clk_rate;
		byte_intf_clk_div = host_cfg->byte_intf_clk_div;
		do_div(byte_intf_clk_rate, byte_intf_clk_div);

		config->bit_clk_rate_hz = byte_clk_rate * 8;
		} else {
		do_div(bit_rate, bits_per_symbol);
		bit_rate *= num_of_symbols;
		bit_rate_per_lane = bit_rate;
		do_div(bit_rate_per_lane, num_of_lanes);
		byte_clk_rate = bit_rate_per_lane;
		do_div(byte_clk_rate, 7);
		/* For CPHY, byte_intf_clk is same as byte_clk */
		byte_intf_clk_rate = byte_clk_rate;
		config->bit_clk_rate_hz = byte_clk_rate * 7;
		}
		DSI_CTRL_DEBUG(dsi_ctrl, "bit_clk_rate = %llu, bit_clk_rate_per_lane = %llu\n",
		bit_rate, bit_rate_per_lane);
		DSI_CTRL_DEBUG(dsi_ctrl, "byte_clk_rate = %llu, byte_intf_clk = %llu\n",
		@@ -938,10 +956,9 @@ static int dsi_ctrl_update_link_freqs(struct dsi_ctrl *dsi_ctrl,
		DSI_CTRL_DEBUG(dsi_ctrl, "pclk_rate = %llu\n", pclk_rate);

		dsi_ctrl->clk_freq.byte_clk_rate = byte_clk_rate;
		dsi_ctrl->clk_freq.byte_intf_clk_rate = byte_intf_clk_rate;
		dsi_ctrl->clk_freq.pix_clk_rate = pclk_rate;
		dsi_ctrl->clk_freq.esc_clk_rate = config->esc_clk_rate_hz;
		dsi_ctrl->clk_freq.byte_intf_clk_rate = byte_intf_clk_rate;
		config->bit_clk_rate_hz = dsi_ctrl->clk_freq.byte_clk_rate * 8;

		rc = dsi_clk_set_link_frequencies(clk_handle, dsi_ctrl->clk_freq,
		dsi_ctrl->cell_index);

msm/dsi/dsi_ctrl_hw_cmn.c

+3 −0

Original line number	Diff line number	Diff line
		@@ -117,6 +117,9 @@ void dsi_ctrl_hw_cmn_host_setup(struct dsi_ctrl_hw *ctrl,

		DSI_W32(ctrl, DSI_CTRL, reg_value);

		if (cfg->phy_type == DSI_PHY_TYPE_CPHY)
		DSI_W32(ctrl, DSI_CPHY_MODE_CTRL, BIT(0));

		if (ctrl->phy_isolation_enabled)
		DSI_W32(ctrl, DSI_DEBUG_CTRL, BIT(28));
		DSI_CTRL_HW_DBG(ctrl, "Host configuration complete\n");

msm/dsi/dsi_ctrl_reg.h

+1 −0

Original line number	Diff line number	Diff line
		@@ -144,6 +144,7 @@
		#define DSI_SECURE_DISPLAY_STATUS (0x02CC)
		#define DSI_SECURE_DISPLAY_BLOCK_COMMAND_COLOR (0x02D0)
		#define DSI_SECURE_DISPLAY_BLOCK_VIDEO_COLOR (0x02D4)
		#define DSI_CPHY_MODE_CTRL (0x02D8)
		#define DSI_LOGICAL_LANE_SWAP_CTRL (0x0310)
		#define DSI_SPLIT_LINK (0x0330)

msm/dsi/dsi_defs.h

+2 −0

Original line number	Diff line number	Diff line
		@@ -484,6 +484,7 @@ struct dsi_split_link_config {
		* true.
		* @ext_bridge_mode: External bridge is connected.
		* @force_hs_clk_lane: Send continuous clock to the panel.
		* @phy_type: DPHY/CPHY is enabled for this panel.
		* @dsi_split_link_config: Split Link Configuration.
		* @byte_intf_clk_div: Determines the factor for calculating byte intf clock.
		*/
		@@ -508,6 +509,7 @@ struct dsi_host_common_cfg {
		bool append_tx_eot;
		bool ext_bridge_mode;
		bool force_hs_clk_lane;
		enum dsi_phy_type phy_type;
		struct dsi_split_link_config split_link;
		u32 byte_intf_clk_div;
		};

msm/dsi/dsi_display.c

+63 −8

Original line number	Diff line number	Diff line
		@@ -2296,6 +2296,20 @@ static int dsi_display_set_clk_src(struct dsi_display *display)
		int i;
		struct dsi_display_ctrl m_ctrl, ctrl;

		/*
		* For CPHY mode, the parent of mux_clks need to be set
		* to Cphy_clks to have correct dividers for byte and
		* pixel clocks.
		*/
		if (display->panel->host_config.phy_type == DSI_PHY_TYPE_CPHY) {
		rc = dsi_clk_update_parent(&display->clock_info.cphy_clks,
		&display->clock_info.mux_clks);
		if (rc) {
		DSI_ERR("failed update mux parent to shadow\n");
		return rc;
		}
		}

		/*
		* In case of split DSI usecases, the clock for master controller should
		* be enabled before the other controller. Master controller in the
		@@ -2362,8 +2376,12 @@ static void dsi_display_toggle_resync_fifo(struct dsi_display *display)

		/*
		* After retime buffer synchronization we need to turn of clk_en_sel
		* bit on each phy.
		* bit on each phy. Avoid this for Cphy.
		*/

		if (display->panel->host_config.phy_type == DSI_PHY_TYPE_CPHY)
		return;

		display_for_each_ctrl(i, display) {
		ctrl = &display->ctrl[i];
		dsi_phy_reset_clk_en_sel(ctrl->phy);
		@@ -3018,10 +3036,12 @@ static int dsi_display_clocks_init(struct dsi_display *display)
		const char *clk_name;
		const char src_byte = "src_byte", src_pixel = "src_pixel";
		const char mux_byte = "mux_byte", mux_pixel = "mux_pixel";
		const char cphy_byte = "cphy_byte", cphy_pixel = "cphy_pixel";
		const char shadow_byte = "shadow_byte", shadow_pixel = "shadow_pixel";
		struct clk *dsi_clk;
		struct dsi_clk_link_set *src = &display->clock_info.src_clks;
		struct dsi_clk_link_set *mux = &display->clock_info.mux_clks;
		struct dsi_clk_link_set *cphy = &display->clock_info.cphy_clks;
		struct dsi_clk_link_set *shadow = &display->clock_info.shadow_clks;
		struct dsi_dyn_clk_caps *dyn_clk_caps = &(display->panel->dyn_clk_caps);
		char *dsi_clock_name;
		@@ -3056,6 +3076,15 @@ static int dsi_display_clocks_init(struct dsi_display *display)
		goto error;
		}

		if (dsi_display_check_prefix(cphy_byte, clk_name)) {
		cphy->byte_clk = NULL;
		goto error;
		}
		if (dsi_display_check_prefix(cphy_pixel, clk_name)) {
		cphy->pixel_clk = NULL;
		goto error;
		}

		if (dyn_clk_caps->dyn_clk_support &&
		(display->panel->panel_mode ==
		DSI_OP_VIDEO_MODE)) {
		@@ -3087,6 +3116,16 @@ static int dsi_display_clocks_init(struct dsi_display *display)
		continue;
		}

		if (dsi_display_check_prefix(cphy_byte, clk_name)) {
		cphy->byte_clk = dsi_clk;
		continue;
		}

		if (dsi_display_check_prefix(cphy_pixel, clk_name)) {
		cphy->pixel_clk = dsi_clk;
		continue;
		}

		if (dsi_display_check_prefix(mux_byte, clk_name)) {
		mux->byte_clk = dsi_clk;
		continue;
		@@ -3709,6 +3748,8 @@ static int dsi_display_res_init(struct dsi_display *display)

		phy->cfg.force_clk_lane_hs =
		display->panel->host_config.force_hs_clk_lane;
		phy->cfg.phy_type =
		display->panel->host_config.phy_type;
		}

		rc = dsi_display_parse_lane_map(display);
		@@ -3922,6 +3963,7 @@ static int dsi_display_update_dsi_bitrate(struct dsi_display *display,
		u32 num_of_lanes = 0, bpp, byte_intf_clk_div;
		u64 bit_rate, pclk_rate, bit_rate_per_lane, byte_clk_rate,
		byte_intf_clk_rate;
		u32 bits_per_symbol = 16, num_of_symbols = 7; /* For Cphy */
		struct dsi_host_common_cfg *host_cfg;

		mutex_lock(&ctrl->ctrl_lock);
		@@ -3949,11 +3991,24 @@ static int dsi_display_update_dsi_bitrate(struct dsi_display *display,
		do_div(bit_rate_per_lane, num_of_lanes);
		pclk_rate = bit_rate;
		do_div(pclk_rate, bpp);
		if (host_cfg->phy_type == DSI_PHY_TYPE_DPHY) {
		bit_rate_per_lane = bit_rate;
		do_div(bit_rate_per_lane, num_of_lanes);
		byte_clk_rate = bit_rate_per_lane;
		do_div(byte_clk_rate, 8);
		byte_intf_clk_rate = byte_clk_rate;
		byte_intf_clk_div = host_cfg->byte_intf_clk_div;
		do_div(byte_intf_clk_rate, byte_intf_clk_div);
		} else {
		do_div(bit_rate, bits_per_symbol);
		bit_rate *= num_of_symbols;
		bit_rate_per_lane = bit_rate;
		do_div(bit_rate_per_lane, num_of_lanes);
		byte_clk_rate = bit_rate_per_lane;
		do_div(byte_clk_rate, 7);
		/* For CPHY, byte_intf_clk is same as byte_clk */
		byte_intf_clk_rate = byte_clk_rate;
		}

		DSI_DEBUG("bit_clk_rate = %llu, bit_clk_rate_per_lane = %llu\n",
		bit_rate, bit_rate_per_lane);