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Commit a851ea2b authored by Alex Frid's avatar Alex Frid Committed by Stephen Boyd
Browse files

clk: tegra: Fix T210 effective NDIV calculation 



Don't take the fractional part into account to calculate the effective
NDIV if fractional ndiv is not enabled.

Signed-off-by: default avatarAlex Frid <afrid@nvidia.com>
Signed-off-by: default avatarPeter De Schrijver <pdeschrijver@nvidia.com>
Tested-by: default avatarThierry Reding <treding@nvidia.com>
Acked-by: default avatarThierry Reding <treding@nvidia.com>
Signed-off-by: default avatarStephen Boyd <sboyd@codeaurora.org>
parent bc7b34a2

drivers/clk/tegra/clk-tegra210.c

+5 −4
Original line number Diff line number Diff line
@@ -241,6 +241,9 @@ 
#define PLL_SDM_COEFF BIT(13)

#define sdin_din_to_data(din)	((u16)((din) ? : 0xFFFFU))

#define sdin_data_to_din(dat)	(((dat) == 0xFFFFU) ? 0 : (s16)dat)

/* This macro returns ndiv effective scaled to SDM range */

#define sdin_get_n_eff(cfg)	((cfg)->n * PLL_SDM_COEFF + ((cfg)->sdm_data ? \

		(PLL_SDM_COEFF/2 + sdin_data_to_din((cfg)->sdm_data)) : 0))



/* Tegra CPU clock and reset control regs */

#define CLK_RST_CONTROLLER_CPU_CMPLX_STATUS	0x470
@@ -1288,8 +1291,7 @@ static int tegra210_pll_fixed_mdiv_cfg(struct clk_hw *hw, 
			s -= PLL_SDM_COEFF / 2;

			cfg->sdm_data = sdin_din_to_data(s);

		}

		cfg->output_rate *= cfg->n * PLL_SDM_COEFF + PLL_SDM_COEFF/2 +

					sdin_data_to_din(cfg->sdm_data);

		cfg->output_rate *= sdin_get_n_eff(cfg);

		cfg->output_rate /= p * cfg->m * PLL_SDM_COEFF;

	} else {

		cfg->output_rate *= cfg->n;
@@ -1314,8 +1316,7 @@ static int tegra210_pll_fixed_mdiv_cfg(struct clk_hw *hw, 
 */

static void tegra210_clk_pll_set_gain(struct tegra_clk_pll_freq_table *cfg)

{

	cfg->n = cfg->n * PLL_SDM_COEFF + PLL_SDM_COEFF/2 +

			sdin_data_to_din(cfg->sdm_data);

	cfg->n = sdin_get_n_eff(cfg);

	cfg->m *= PLL_SDM_COEFF;

}