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Commit a7c5047d authored by Eric Anholt's avatar Eric Anholt
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drm/vc4: Fix setting of vertical timings in the CRTC.



It looks like when I went to add the interlaced bits, I just took the
existing PV_VERT* block and indented it, instead of copy and pasting
it first.  Without this, changing resolution never worked.

Signed-off-by: default avatarEric Anholt <eric@anholt.net>
parent c31806fb
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