igb: use BIT() macro or unsigned prefix (a51d8c21) · Commits · e / devices / android_kernel_fairphone_FP4

drivers/net/ethernet/intel/igb/e1000_82575.c

+4 −4

Original line number	Diff line number	Diff line
		@@ -361,7 +361,7 @@ static s32 igb_init_nvm_params_82575(struct e1000_hw *hw)
		if (size > 15)
		size = 15;

		nvm->word_size = 1 << size;
		nvm->word_size = BIT(size);
		nvm->opcode_bits = 8;
		nvm->delay_usec = 1;

		@@ -380,7 +380,7 @@ static s32 igb_init_nvm_params_82575(struct e1000_hw *hw)
		16 : 8;
		break;
		}
		if (nvm->word_size == (1 << 15))
		if (nvm->word_size == BIT(15))
		nvm->page_size = 128;

		nvm->type = e1000_nvm_eeprom_spi;
		@@ -391,7 +391,7 @@ static s32 igb_init_nvm_params_82575(struct e1000_hw *hw)
		nvm->ops.write = igb_write_nvm_spi;
		nvm->ops.validate = igb_validate_nvm_checksum;
		nvm->ops.update = igb_update_nvm_checksum;
		if (nvm->word_size < (1 << 15))
		if (nvm->word_size < BIT(15))
		nvm->ops.read = igb_read_nvm_eerd;
		else
		nvm->ops.read = igb_read_nvm_spi;
		@@ -2107,7 +2107,7 @@ void igb_vmdq_set_anti_spoofing_pf(struct e1000_hw *hw, bool enable, int pf)
		/* The PF can spoof - it has to in order to
		* support emulation mode NICs
		*/
		reg_val ^= (1 << pf \| 1 << (pf + MAX_NUM_VFS));
		reg_val ^= (BIT(pf) \| BIT(pf + MAX_NUM_VFS));
		} else {
		reg_val &= ~(E1000_DTXSWC_MAC_SPOOF_MASK \|
		E1000_DTXSWC_VLAN_SPOOF_MASK);

drivers/net/ethernet/intel/igb/e1000_82575.h

+15 −15

Original line number	Diff line number	Diff line
		@@ -168,16 +168,16 @@ struct e1000_adv_tx_context_desc {
		#define E1000_DCA_CTRL_DCA_MODE_CB2 0x02 /* DCA Mode CB2 */

		#define E1000_DCA_RXCTRL_CPUID_MASK 0x0000001F /* Rx CPUID Mask */
		#define E1000_DCA_RXCTRL_DESC_DCA_EN (1 << 5) /* DCA Rx Desc enable */
		#define E1000_DCA_RXCTRL_HEAD_DCA_EN (1 << 6) /* DCA Rx Desc header enable */
		#define E1000_DCA_RXCTRL_DATA_DCA_EN (1 << 7) /* DCA Rx Desc payload enable */
		#define E1000_DCA_RXCTRL_DESC_RRO_EN (1 << 9) /* DCA Rx rd Desc Relax Order */
		#define E1000_DCA_RXCTRL_DESC_DCA_EN BIT(5) /* DCA Rx Desc enable */
		#define E1000_DCA_RXCTRL_HEAD_DCA_EN BIT(6) /* DCA Rx Desc header enable */
		#define E1000_DCA_RXCTRL_DATA_DCA_EN BIT(7) /* DCA Rx Desc payload enable */
		#define E1000_DCA_RXCTRL_DESC_RRO_EN BIT(9) /* DCA Rx rd Desc Relax Order */

		#define E1000_DCA_TXCTRL_CPUID_MASK 0x0000001F /* Tx CPUID Mask */
		#define E1000_DCA_TXCTRL_DESC_DCA_EN (1 << 5) /* DCA Tx Desc enable */
		#define E1000_DCA_TXCTRL_DESC_RRO_EN (1 << 9) /* Tx rd Desc Relax Order */
		#define E1000_DCA_TXCTRL_TX_WB_RO_EN (1 << 11) /* Tx Desc writeback RO bit */
		#define E1000_DCA_TXCTRL_DATA_RRO_EN (1 << 13) /* Tx rd data Relax Order */
		#define E1000_DCA_TXCTRL_DESC_DCA_EN BIT(5) /* DCA Tx Desc enable */
		#define E1000_DCA_TXCTRL_DESC_RRO_EN BIT(9) /* Tx rd Desc Relax Order */
		#define E1000_DCA_TXCTRL_TX_WB_RO_EN BIT(11) /* Tx Desc writeback RO bit */
		#define E1000_DCA_TXCTRL_DATA_RRO_EN BIT(13) /* Tx rd data Relax Order */

		/* Additional DCA related definitions, note change in position of CPUID */
		#define E1000_DCA_TXCTRL_CPUID_MASK_82576 0xFF000000 /* Tx CPUID Mask */
		@@ -186,8 +186,8 @@ struct e1000_adv_tx_context_desc {
		#define E1000_DCA_RXCTRL_CPUID_SHIFT 24 /* Rx CPUID now in the last byte */

		/* ETQF register bit definitions */
		#define E1000_ETQF_FILTER_ENABLE (1 << 26)
		#define E1000_ETQF_1588 (1 << 30)
		#define E1000_ETQF_FILTER_ENABLE BIT(26)
		#define E1000_ETQF_1588 BIT(30)

		/* FTQF register bit definitions */
		#define E1000_FTQF_VF_BP 0x00008000
		@@ -203,16 +203,16 @@ struct e1000_adv_tx_context_desc {
		#define E1000_DTXSWC_VLAN_SPOOF_MASK 0x0000FF00 /* Per VF VLAN spoof control */
		#define E1000_DTXSWC_LLE_MASK 0x00FF0000 /* Per VF Local LB enables */
		#define E1000_DTXSWC_VLAN_SPOOF_SHIFT 8
		#define E1000_DTXSWC_VMDQ_LOOPBACK_EN (1 << 31) /* global VF LB enable */
		#define E1000_DTXSWC_VMDQ_LOOPBACK_EN BIT(31) /* global VF LB enable */

		/* Easy defines for setting default pool, would normally be left a zero */
		#define E1000_VT_CTL_DEFAULT_POOL_SHIFT 7
		#define E1000_VT_CTL_DEFAULT_POOL_MASK (0x7 << E1000_VT_CTL_DEFAULT_POOL_SHIFT)

		/* Other useful VMD_CTL register defines */
		#define E1000_VT_CTL_IGNORE_MAC (1 << 28)
		#define E1000_VT_CTL_DISABLE_DEF_POOL (1 << 29)
		#define E1000_VT_CTL_VM_REPL_EN (1 << 30)
		#define E1000_VT_CTL_IGNORE_MAC BIT(28)
		#define E1000_VT_CTL_DISABLE_DEF_POOL BIT(29)
		#define E1000_VT_CTL_VM_REPL_EN BIT(30)

		/* Per VM Offload register setup */
		#define E1000_VMOLR_RLPML_MASK 0x00003FFF /* Long Packet Maximum Length mask */
		@@ -252,7 +252,7 @@ struct e1000_adv_tx_context_desc {
		#define E1000_DTXCTL_MDP_EN 0x0020
		#define E1000_DTXCTL_SPOOF_INT 0x0040

		#define E1000_EEPROM_PCS_AUTONEG_DISABLE_BIT (1 << 14)
		#define E1000_EEPROM_PCS_AUTONEG_DISABLE_BIT BIT(14)

		#define ALL_QUEUES 0xFFFF

drivers/net/ethernet/intel/igb/e1000_defines.h

+54 −54

Original line number	Diff line number	Diff line
		@@ -530,65 +530,65 @@

		/* Time Sync Interrupt Cause/Mask Register Bits */

		#define TSINTR_SYS_WRAP (1 << 0) /* SYSTIM Wrap around. */
		#define TSINTR_TXTS (1 << 1) /* Transmit Timestamp. */
		#define TSINTR_RXTS (1 << 2) /* Receive Timestamp. */
		#define TSINTR_TT0 (1 << 3) /* Target Time 0 Trigger. */
		#define TSINTR_TT1 (1 << 4) /* Target Time 1 Trigger. */
		#define TSINTR_AUTT0 (1 << 5) /* Auxiliary Timestamp 0 Taken. */
		#define TSINTR_AUTT1 (1 << 6) /* Auxiliary Timestamp 1 Taken. */
		#define TSINTR_TADJ (1 << 7) /* Time Adjust Done. */
		#define TSINTR_SYS_WRAP BIT(0) /* SYSTIM Wrap around. */
		#define TSINTR_TXTS BIT(1) /* Transmit Timestamp. */
		#define TSINTR_RXTS BIT(2) /* Receive Timestamp. */
		#define TSINTR_TT0 BIT(3) /* Target Time 0 Trigger. */
		#define TSINTR_TT1 BIT(4) /* Target Time 1 Trigger. */
		#define TSINTR_AUTT0 BIT(5) /* Auxiliary Timestamp 0 Taken. */
		#define TSINTR_AUTT1 BIT(6) /* Auxiliary Timestamp 1 Taken. */
		#define TSINTR_TADJ BIT(7) /* Time Adjust Done. */

		#define TSYNC_INTERRUPTS TSINTR_TXTS
		#define E1000_TSICR_TXTS TSINTR_TXTS

		/* TSAUXC Configuration Bits */
		#define TSAUXC_EN_TT0 (1 << 0) /* Enable target time 0. */
		#define TSAUXC_EN_TT1 (1 << 1) /* Enable target time 1. */
		#define TSAUXC_EN_CLK0 (1 << 2) /* Enable Configurable Frequency Clock 0. */
		#define TSAUXC_SAMP_AUT0 (1 << 3) /* Latch SYSTIML/H into AUXSTMPL/0. */
		#define TSAUXC_ST0 (1 << 4) /* Start Clock 0 Toggle on Target Time 0. */
		#define TSAUXC_EN_CLK1 (1 << 5) /* Enable Configurable Frequency Clock 1. */
		#define TSAUXC_SAMP_AUT1 (1 << 6) /* Latch SYSTIML/H into AUXSTMPL/1. */
		#define TSAUXC_ST1 (1 << 7) /* Start Clock 1 Toggle on Target Time 1. */
		#define TSAUXC_EN_TS0 (1 << 8) /* Enable hardware timestamp 0. */
		#define TSAUXC_AUTT0 (1 << 9) /* Auxiliary Timestamp Taken. */
		#define TSAUXC_EN_TS1 (1 << 10) /* Enable hardware timestamp 0. */
		#define TSAUXC_AUTT1 (1 << 11) /* Auxiliary Timestamp Taken. */
		#define TSAUXC_PLSG (1 << 17) /* Generate a pulse. */
		#define TSAUXC_DISABLE (1 << 31) /* Disable SYSTIM Count Operation. */
		#define TSAUXC_EN_TT0 BIT(0) /* Enable target time 0. */
		#define TSAUXC_EN_TT1 BIT(1) /* Enable target time 1. */
		#define TSAUXC_EN_CLK0 BIT(2) /* Enable Configurable Frequency Clock 0. */
		#define TSAUXC_SAMP_AUT0 BIT(3) /* Latch SYSTIML/H into AUXSTMPL/0. */
		#define TSAUXC_ST0 BIT(4) /* Start Clock 0 Toggle on Target Time 0. */
		#define TSAUXC_EN_CLK1 BIT(5) /* Enable Configurable Frequency Clock 1. */
		#define TSAUXC_SAMP_AUT1 BIT(6) /* Latch SYSTIML/H into AUXSTMPL/1. */
		#define TSAUXC_ST1 BIT(7) /* Start Clock 1 Toggle on Target Time 1. */
		#define TSAUXC_EN_TS0 BIT(8) /* Enable hardware timestamp 0. */
		#define TSAUXC_AUTT0 BIT(9) /* Auxiliary Timestamp Taken. */
		#define TSAUXC_EN_TS1 BIT(10) /* Enable hardware timestamp 0. */
		#define TSAUXC_AUTT1 BIT(11) /* Auxiliary Timestamp Taken. */
		#define TSAUXC_PLSG BIT(17) /* Generate a pulse. */
		#define TSAUXC_DISABLE BIT(31) /* Disable SYSTIM Count Operation. */

		/* SDP Configuration Bits */
		#define AUX0_SEL_SDP0 (0 << 0) /* Assign SDP0 to auxiliary time stamp 0. */
		#define AUX0_SEL_SDP1 (1 << 0) /* Assign SDP1 to auxiliary time stamp 0. */
		#define AUX0_SEL_SDP2 (2 << 0) /* Assign SDP2 to auxiliary time stamp 0. */
		#define AUX0_SEL_SDP3 (3 << 0) /* Assign SDP3 to auxiliary time stamp 0. */
		#define AUX0_TS_SDP_EN (1 << 2) /* Enable auxiliary time stamp trigger 0. */
		#define AUX1_SEL_SDP0 (0 << 3) /* Assign SDP0 to auxiliary time stamp 1. */
		#define AUX1_SEL_SDP1 (1 << 3) /* Assign SDP1 to auxiliary time stamp 1. */
		#define AUX1_SEL_SDP2 (2 << 3) /* Assign SDP2 to auxiliary time stamp 1. */
		#define AUX1_SEL_SDP3 (3 << 3) /* Assign SDP3 to auxiliary time stamp 1. */
		#define AUX1_TS_SDP_EN (1 << 5) /* Enable auxiliary time stamp trigger 1. */
		#define TS_SDP0_SEL_TT0 (0 << 6) /* Target time 0 is output on SDP0. */
		#define TS_SDP0_SEL_TT1 (1 << 6) /* Target time 1 is output on SDP0. */
		#define TS_SDP0_SEL_FC0 (2 << 6) /* Freq clock 0 is output on SDP0. */
		#define TS_SDP0_SEL_FC1 (3 << 6) /* Freq clock 1 is output on SDP0. */
		#define TS_SDP0_EN (1 << 8) /* SDP0 is assigned to Tsync. */
		#define TS_SDP1_SEL_TT0 (0 << 9) /* Target time 0 is output on SDP1. */
		#define TS_SDP1_SEL_TT1 (1 << 9) /* Target time 1 is output on SDP1. */
		#define TS_SDP1_SEL_FC0 (2 << 9) /* Freq clock 0 is output on SDP1. */
		#define TS_SDP1_SEL_FC1 (3 << 9) /* Freq clock 1 is output on SDP1. */
		#define TS_SDP1_EN (1 << 11) /* SDP1 is assigned to Tsync. */
		#define TS_SDP2_SEL_TT0 (0 << 12) /* Target time 0 is output on SDP2. */
		#define TS_SDP2_SEL_TT1 (1 << 12) /* Target time 1 is output on SDP2. */
		#define TS_SDP2_SEL_FC0 (2 << 12) /* Freq clock 0 is output on SDP2. */
		#define TS_SDP2_SEL_FC1 (3 << 12) /* Freq clock 1 is output on SDP2. */
		#define TS_SDP2_EN (1 << 14) /* SDP2 is assigned to Tsync. */
		#define TS_SDP3_SEL_TT0 (0 << 15) /* Target time 0 is output on SDP3. */
		#define TS_SDP3_SEL_TT1 (1 << 15) /* Target time 1 is output on SDP3. */
		#define TS_SDP3_SEL_FC0 (2 << 15) /* Freq clock 0 is output on SDP3. */
		#define TS_SDP3_SEL_FC1 (3 << 15) /* Freq clock 1 is output on SDP3. */
		#define TS_SDP3_EN (1 << 17) /* SDP3 is assigned to Tsync. */
		#define AUX0_SEL_SDP0 (0u << 0) /* Assign SDP0 to auxiliary time stamp 0. */
		#define AUX0_SEL_SDP1 (1u << 0) /* Assign SDP1 to auxiliary time stamp 0. */
		#define AUX0_SEL_SDP2 (2u << 0) /* Assign SDP2 to auxiliary time stamp 0. */
		#define AUX0_SEL_SDP3 (3u << 0) /* Assign SDP3 to auxiliary time stamp 0. */
		#define AUX0_TS_SDP_EN (1u << 2) /* Enable auxiliary time stamp trigger 0. */
		#define AUX1_SEL_SDP0 (0u << 3) /* Assign SDP0 to auxiliary time stamp 1. */
		#define AUX1_SEL_SDP1 (1u << 3) /* Assign SDP1 to auxiliary time stamp 1. */
		#define AUX1_SEL_SDP2 (2u << 3) /* Assign SDP2 to auxiliary time stamp 1. */
		#define AUX1_SEL_SDP3 (3u << 3) /* Assign SDP3 to auxiliary time stamp 1. */
		#define AUX1_TS_SDP_EN (1u << 5) /* Enable auxiliary time stamp trigger 1. */
		#define TS_SDP0_SEL_TT0 (0u << 6) /* Target time 0 is output on SDP0. */
		#define TS_SDP0_SEL_TT1 (1u << 6) /* Target time 1 is output on SDP0. */
		#define TS_SDP0_SEL_FC0 (2u << 6) /* Freq clock 0 is output on SDP0. */
		#define TS_SDP0_SEL_FC1 (3u << 6) /* Freq clock 1 is output on SDP0. */
		#define TS_SDP0_EN (1u << 8) /* SDP0 is assigned to Tsync. */
		#define TS_SDP1_SEL_TT0 (0u << 9) /* Target time 0 is output on SDP1. */
		#define TS_SDP1_SEL_TT1 (1u << 9) /* Target time 1 is output on SDP1. */
		#define TS_SDP1_SEL_FC0 (2u << 9) /* Freq clock 0 is output on SDP1. */
		#define TS_SDP1_SEL_FC1 (3u << 9) /* Freq clock 1 is output on SDP1. */
		#define TS_SDP1_EN (1u << 11) /* SDP1 is assigned to Tsync. */
		#define TS_SDP2_SEL_TT0 (0u << 12) /* Target time 0 is output on SDP2. */
		#define TS_SDP2_SEL_TT1 (1u << 12) /* Target time 1 is output on SDP2. */
		#define TS_SDP2_SEL_FC0 (2u << 12) /* Freq clock 0 is output on SDP2. */
		#define TS_SDP2_SEL_FC1 (3u << 12) /* Freq clock 1 is output on SDP2. */
		#define TS_SDP2_EN (1u << 14) /* SDP2 is assigned to Tsync. */
		#define TS_SDP3_SEL_TT0 (0u << 15) /* Target time 0 is output on SDP3. */
		#define TS_SDP3_SEL_TT1 (1u << 15) /* Target time 1 is output on SDP3. */
		#define TS_SDP3_SEL_FC0 (2u << 15) /* Freq clock 0 is output on SDP3. */
		#define TS_SDP3_SEL_FC1 (3u << 15) /* Freq clock 1 is output on SDP3. */
		#define TS_SDP3_EN (1u << 17) /* SDP3 is assigned to Tsync. */

		#define E1000_MDICNFG_EXT_MDIO 0x80000000 /* MDI ext/int destination */
		#define E1000_MDICNFG_COM_MDIO 0x40000000 /* MDI shared w/ lan 0 */
		@@ -997,8 +997,8 @@
		#define E1000_M88E1543_FIBER_CTRL 0x0
		#define E1000_EEE_ADV_DEV_I354 7
		#define E1000_EEE_ADV_ADDR_I354 60
		#define E1000_EEE_ADV_100_SUPPORTED (1 << 1) /* 100BaseTx EEE Supported */
		#define E1000_EEE_ADV_1000_SUPPORTED (1 << 2) /* 1000BaseT EEE Supported */
		#define E1000_EEE_ADV_100_SUPPORTED BIT(1) /* 100BaseTx EEE Supported */
		#define E1000_EEE_ADV_1000_SUPPORTED BIT(2) /* 1000BaseT EEE Supported */
		#define E1000_PCS_STATUS_DEV_I354 3
		#define E1000_PCS_STATUS_ADDR_I354 1
		#define E1000_PCS_STATUS_TX_LPI_IND 0x0200 /* Tx in LPI state */

drivers/net/ethernet/intel/igb/e1000_mac.c

+5 −5

Original line number	Diff line number	Diff line
		@@ -212,7 +212,7 @@ s32 igb_vfta_set(struct e1000_hw *hw, u32 vlan, u32 vind,
		* bits[4-0]: which bit in the register
		*/
		regidx = vlan / 32;
		vfta_delta = 1 << (vlan % 32);
		vfta_delta = BIT(vlan % 32);
		vfta = adapter->shadow_vfta[regidx];

		/* vfta_delta represents the difference between the current value
		@@ -243,12 +243,12 @@ s32 igb_vfta_set(struct e1000_hw *hw, u32 vlan, u32 vind,
		bits = rd32(E1000_VLVF(vlvf_index));

		/* set the pool bit */
		bits \|= 1 << (E1000_VLVF_POOLSEL_SHIFT + vind);
		bits \|= BIT(E1000_VLVF_POOLSEL_SHIFT + vind);
		if (vlan_on)
		goto vlvf_update;

		/* clear the pool bit */
		bits ^= 1 << (E1000_VLVF_POOLSEL_SHIFT + vind);
		bits ^= BIT(E1000_VLVF_POOLSEL_SHIFT + vind);

		if (!(bits & E1000_VLVF_POOLSEL_MASK)) {
		/* Clear VFTA first, then disable VLVF. Otherwise
		@@ -427,7 +427,7 @@ void igb_mta_set(struct e1000_hw *hw, u32 hash_value)

		mta = array_rd32(E1000_MTA, hash_reg);

		mta \|= (1 << hash_bit);
		mta \|= BIT(hash_bit);

		array_wr32(E1000_MTA, hash_reg, mta);
		wrfl();
		@@ -527,7 +527,7 @@ void igb_update_mc_addr_list(struct e1000_hw *hw,
		hash_reg = (hash_value >> 5) & (hw->mac.mta_reg_count - 1);
		hash_bit = hash_value & 0x1F;

		hw->mac.mta_shadow[hash_reg] \|= (1 << hash_bit);
		hw->mac.mta_shadow[hash_reg] \|= BIT(hash_bit);
		mc_addr_list += (ETH_ALEN);
		}

drivers/net/ethernet/intel/igb/e1000_mbx.c

+2 −2

Original line number	Diff line number	Diff line
		@@ -302,9 +302,9 @@ static s32 igb_check_for_rst_pf(struct e1000_hw *hw, u16 vf_number)
		u32 vflre = rd32(E1000_VFLRE);
		s32 ret_val = -E1000_ERR_MBX;

		if (vflre & (1 << vf_number)) {
		if (vflre & BIT(vf_number)) {
		ret_val = 0;
		wr32(E1000_VFLRE, (1 << vf_number));
		wr32(E1000_VFLRE, BIT(vf_number));
		hw->mbx.stats.rsts++;
		}