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Commit a4fdb2a4 authored by Linus Torvalds's avatar Linus Torvalds
Browse files

Merge tag 'arm64-upstream' of git://git.kernel.org/pub/scm/linux/kernel/git/arm64/linux 

Pull arm64 updates from Will Deacon:

 - Support for new architectural features introduced in ARMv8.1:
   * Privileged Access Never (PAN) to catch user pointer dereferences in
     the kernel
   * Large System Extension (LSE) for building scalable atomics and locks
     (depends on locking/arch-atomic from tip, which is included here)
   * Hardware Dirty Bit Management (DBM) for updating clean PTEs
     automatically

 - Move our PSCI implementation out into drivers/firmware/, where it can
   be shared with arch/arm/. RMK has also pulled this component branch
   and has additional patches moving arch/arm/ over. MAINTAINERS is
   updated accordingly.

 - Better BUG implementation based on the BRK instruction for trapping

 - Leaf TLB invalidation for unmapping user pages

 - Support for PROBE_ONLY PCI configurations

 - Various cleanups and non-critical fixes, including:
   * Always flush FP/SIMD state over exec()
   * Restrict memblock additions based on range of linear mapping
   * Ensure *(LIST_POISON) generates a fatal fault
   * Context-tracking syscall return no longer corrupts return value when
     not forced on.
   * Alternatives patching synchronisation/stability improvements
   * Signed sub-word cmpxchg compare fix (tickled by HAVE_CMPXCHG_LOCAL)
   * Force SMP=y
   * Hide direct DCC access from userspace
   * Fix EFI stub memory allocation when DRAM starts at 0x0

* tag 'arm64-upstream' of git://git.kernel.org/pub/scm/linux/kernel/git/arm64/linux: (92 commits)
  arm64: flush FP/SIMD state correctly after execve()
  arm64: makefile: fix perf_callchain.o kconfig dependency
  arm64: set MAX_MEMBLOCK_ADDR according to linear region size
  of/fdt: make memblock maximum physical address arch configurable
  arm64: Fix source code file path in comments
  arm64: entry: always restore x0 from the stack on syscall return
  arm64: mdscr_el1: avoid exposing DCC to userspace
  arm64: kconfig: Move LIST_POISON to a safe value
  arm64: Add __exception_irq_entry definition for function graph
  arm64: mm: ensure patched kernel text is fetched from PoU
  arm64: alternatives: ensure secondary CPUs execute ISB after patching
  arm64: make ll/sc __cmpxchg_case_##name asm consistent
  arm64: dma-mapping: Simplify pgprot handling
  arm64: restore cpu suspend/resume functionality
  ARM64: PCI: do not enable resources on PROBE_ONLY systems
  arm64: cmpxchg: truncate sub-word signed types before comparison
  arm64: alternative: put secondary CPUs into polling loop during patch
  arm64/Documentation: clarify wording regarding memory below the Image
  arm64: lse: fix lse cmpxchg code indentation
  arm64: remove redundant object file list
  ...
parents 807249d3 674c242c

Documentation/arm64/booting.txt

+7 −4
Original line number Diff line number Diff line
@@ -115,11 +115,14 @@ The Image must be placed text_offset bytes from a 2MB aligned base 
address near the start of usable system RAM and called there. Memory

below that base address is currently unusable by Linux, and therefore it

is strongly recommended that this location is the start of system RAM.

The region between the 2 MB aligned base address and the start of the

image has no special significance to the kernel, and may be used for

other purposes.

At least image_size bytes from the start of the image must be free for

use by the kernel.



Any memory described to the kernel (even that below the 2MB aligned base

address) which is not marked as reserved from the kernel e.g. with a

Any memory described to the kernel (even that below the start of the

image) which is not marked as reserved from the kernel (e.g., with a

memreserve region in the device tree) will be considered as available to

the kernel.

arch/arm64/Kconfig

+64 −22
Original line number Diff line number Diff line
@@ -29,7 +29,7 @@ config ARM64 
	select EDAC_SUPPORT

	select GENERIC_ALLOCATOR

	select GENERIC_CLOCKEVENTS

	select GENERIC_CLOCKEVENTS_BROADCAST if SMP

	select GENERIC_CLOCKEVENTS_BROADCAST

	select GENERIC_CPU_AUTOPROBE

	select GENERIC_EARLY_IOREMAP

	select GENERIC_IRQ_PROBE
@@ -54,6 +54,7 @@ config ARM64 
	select HAVE_C_RECORDMCOUNT

	select HAVE_CC_STACKPROTECTOR

	select HAVE_CMPXCHG_DOUBLE

	select HAVE_CMPXCHG_LOCAL

	select HAVE_DEBUG_BUGVERBOSE

	select HAVE_DEBUG_KMEMLEAK

	select HAVE_DMA_API_DEBUG
@@ -105,6 +106,10 @@ config NO_IOPORT_MAP 
config STACKTRACE_SUPPORT

	def_bool y



config ILLEGAL_POINTER_VALUE

	hex

	default 0xdead000000000000



config LOCKDEP_SUPPORT

	def_bool y
@@ -114,6 +119,14 @@ config TRACE_IRQFLAGS_SUPPORT 
config RWSEM_XCHGADD_ALGORITHM

	def_bool y



config GENERIC_BUG

	def_bool y

	depends on BUG



config GENERIC_BUG_RELATIVE_POINTERS

	def_bool y

	depends on GENERIC_BUG



config GENERIC_HWEIGHT

	def_bool y
@@ -138,6 +151,9 @@ config NEED_DMA_MAP_STATE 
config NEED_SG_DMA_LENGTH

	def_bool y



config SMP

	def_bool y



config SWIOTLB

	def_bool y
@@ -372,22 +388,8 @@ config CPU_BIG_ENDIAN 
       help

         Say Y if you plan on running a kernel in big-endian mode.



config SMP

	bool "Symmetric Multi-Processing"

	help

	  This enables support for systems with more than one CPU.  If

	  you say N here, the kernel will run on single and

	  multiprocessor machines, but will use only one CPU of a

	  multiprocessor machine. If you say Y here, the kernel will run

	  on many, but not all, single processor machines. On a single

	  processor machine, the kernel will run faster if you say N

	  here.



	  If you don't know what to do here, say N.



config SCHED_MC

	bool "Multi-core scheduler support"

	depends on SMP

	help

	  Multi-core scheduler support improves the CPU scheduler's decision

	  making when dealing with multi-core CPU chips at a cost of slightly
@@ -395,7 +397,6 @@ config SCHED_MC 


config SCHED_SMT

	bool "SMT scheduler support"

	depends on SMP

	help

	  Improves the CPU scheduler's decision making when dealing with

	  MultiThreading at a cost of slightly increased overhead in some
@@ -404,23 +405,17 @@ config SCHED_SMT 
config NR_CPUS

	int "Maximum number of CPUs (2-4096)"

	range 2 4096

	depends on SMP

	# These have to remain sorted largest to smallest

	default "64"



config HOTPLUG_CPU

	bool "Support for hot-pluggable CPUs"

	depends on SMP

	help

	  Say Y here to experiment with turning CPUs off and on.  CPUs

	  can be controlled through /sys/devices/system/cpu.



source kernel/Kconfig.preempt



config UP_LATE_INIT

       def_bool y

       depends on !SMP



config HZ

	int

	default 100
@@ -562,6 +557,53 @@ config SETEND_EMULATION 
	  If unsure, say Y

endif



menu "ARMv8.1 architectural features"



config ARM64_HW_AFDBM

	bool "Support for hardware updates of the Access and Dirty page flags"

	default y

	help

	  The ARMv8.1 architecture extensions introduce support for

	  hardware updates of the access and dirty information in page

	  table entries. When enabled in TCR_EL1 (HA and HD bits) on

	  capable processors, accesses to pages with PTE_AF cleared will

	  set this bit instead of raising an access flag fault.

	  Similarly, writes to read-only pages with the DBM bit set will

	  clear the read-only bit (AP[2]) instead of raising a

	  permission fault.



	  Kernels built with this configuration option enabled continue

	  to work on pre-ARMv8.1 hardware and the performance impact is

	  minimal. If unsure, say Y.



config ARM64_PAN

	bool "Enable support for Privileged Access Never (PAN)"

	default y

	help

	 Privileged Access Never (PAN; part of the ARMv8.1 Extensions)

	 prevents the kernel or hypervisor from accessing user-space (EL0)

	 memory directly.



	 Choosing this option will cause any unprotected (not using

	 copy_to_user et al) memory access to fail with a permission fault.



	 The feature is detected at runtime, and will remain as a 'nop'

	 instruction if the cpu does not implement the feature.



config ARM64_LSE_ATOMICS

	bool "Atomic instructions"

	help

	  As part of the Large System Extensions, ARMv8.1 introduces new

	  atomic instructions that are designed specifically to scale in

	  very large systems.



	  Say Y here to make use of these instructions for the in-kernel

	  atomic routines. This incurs a small overhead on CPUs that do

	  not support these instructions and requires the kernel to be

	  built with binutils >= 2.25.



endmenu



endmenu



menu "Boot options"

arch/arm64/Makefile

+16 −2
Original line number Diff line number Diff line
@@ -17,7 +17,18 @@ GZFLAGS :=-9 


KBUILD_DEFCONFIG := defconfig



KBUILD_CFLAGS	+= -mgeneral-regs-only

# Check for binutils support for specific extensions

lseinstr := $(call as-instr,.arch_extension lse,-DCONFIG_AS_LSE=1)



ifeq ($(CONFIG_ARM64_LSE_ATOMICS), y)

  ifeq ($(lseinstr),)

$(warning LSE atomics not supported by binutils)

  endif

endif



KBUILD_CFLAGS	+= -mgeneral-regs-only $(lseinstr)

KBUILD_AFLAGS	+= $(lseinstr)



ifeq ($(CONFIG_CPU_BIG_ENDIAN), y)

KBUILD_CPPFLAGS	+= -mbig-endian

AS		+= -EB
@@ -58,7 +69,10 @@ all: $(KBUILD_IMAGE) $(KBUILD_DTBS) 


boot := arch/arm64/boot



Image Image.gz: vmlinux

Image: vmlinux

	$(Q)$(MAKE) $(build)=$(boot) $(boot)/$@



Image.%: vmlinux

	$(Q)$(MAKE) $(build)=$(boot) $(boot)/$@



zinstall install: vmlinux

arch/arm64/boot/Makefile

+12 −0
Original line number Diff line number Diff line
@@ -19,9 +19,21 @@ targets := Image Image.gz 
$(obj)/Image: vmlinux FORCE

	$(call if_changed,objcopy)



$(obj)/Image.bz2: $(obj)/Image FORCE

	$(call if_changed,bzip2)



$(obj)/Image.gz: $(obj)/Image FORCE

	$(call if_changed,gzip)



$(obj)/Image.lz4: $(obj)/Image FORCE

	$(call if_changed,lz4)



$(obj)/Image.lzma: $(obj)/Image FORCE

	$(call if_changed,lzma)



$(obj)/Image.lzo: $(obj)/Image FORCE

	$(call if_changed,lzo)



install: $(obj)/Image

	$(CONFIG_SHELL) $(srctree)/$(src)/install.sh $(KERNELRELEASE) \

	$(obj)/Image System.map "$(INSTALL_PATH)"

arch/arm64/include/asm/alternative.h

+74 −4
Original line number Diff line number Diff line
@@ -3,6 +3,8 @@ 


#ifndef __ASSEMBLY__



#include <linux/init.h>

#include <linux/kconfig.h>

#include <linux/types.h>

#include <linux/stddef.h>

#include <linux/stringify.h>
@@ -15,7 +17,7 @@ struct alt_instr { 
	u8  alt_len;		/* size of new instruction(s), <= orig_len */

};



void apply_alternatives_all(void);

void __init apply_alternatives_all(void);

void apply_alternatives(void *start, size_t length);

void free_alternatives_memory(void);
@@ -40,7 +42,8 @@ void free_alternatives_memory(void); 
 * be fixed in a binutils release posterior to 2.25.51.0.2 (anything

 * containing commit 4e4d08cf7399b606 or c1baaddf8861).

 */

#define ALTERNATIVE(oldinstr, newinstr, feature)			\

#define __ALTERNATIVE_CFG(oldinstr, newinstr, feature, cfg_enabled)	\

	".if "__stringify(cfg_enabled)" == 1\n"				\

	"661:\n\t"							\

	oldinstr "\n"							\

	"662:\n"							\
@@ -53,7 +56,11 @@ void free_alternatives_memory(void); 
	"664:\n\t"							\

	".popsection\n\t"						\

	".org	. - (664b-663b) + (662b-661b)\n\t"			\

	".org	. - (662b-661b) + (664b-663b)\n"

	".org	. - (662b-661b) + (664b-663b)\n"			\

	".endif\n"



#define _ALTERNATIVE_CFG(oldinstr, newinstr, feature, cfg, ...)	\

	__ALTERNATIVE_CFG(oldinstr, newinstr, feature, IS_ENABLED(cfg))



#else
@@ -65,7 +72,8 @@ void free_alternatives_memory(void); 
	.byte \alt_len

.endm



.macro alternative_insn insn1 insn2 cap

.macro alternative_insn insn1, insn2, cap, enable = 1

	.if \enable

661:	\insn1

662:	.pushsection .altinstructions, "a"

	altinstruction_entry 661b, 663f, \cap, 662b-661b, 664f-663f
@@ -75,8 +83,70 @@ void free_alternatives_memory(void); 
664:	.popsection

	.org	. - (664b-663b) + (662b-661b)

	.org	. - (662b-661b) + (664b-663b)

	.endif

.endm



/*

 * Begin an alternative code sequence.

 *

 * The code that follows this macro will be assembled and linked as

 * normal. There are no restrictions on this code.

 */

.macro alternative_if_not cap, enable = 1

	.if \enable

	.pushsection .altinstructions, "a"

	altinstruction_entry 661f, 663f, \cap, 662f-661f, 664f-663f

	.popsection

661:

	.endif

.endm



/*

 * Provide the alternative code sequence.

 *

 * The code that follows this macro is assembled into a special

 * section to be used for dynamic patching. Code that follows this

 * macro must:

 *

 * 1. Be exactly the same length (in bytes) as the default code

 *    sequence.

 *

 * 2. Not contain a branch target that is used outside of the

 *    alternative sequence it is defined in (branches into an

 *    alternative sequence are not fixed up).

 */

.macro alternative_else, enable = 1

	.if \enable

662:	.pushsection .altinstr_replacement, "ax"

663:

	.endif

.endm



/*

 * Complete an alternative code sequence.

 */

.macro alternative_endif, enable = 1

	.if \enable

664:	.popsection

	.org	. - (664b-663b) + (662b-661b)

	.org	. - (662b-661b) + (664b-663b)

	.endif

.endm



#define _ALTERNATIVE_CFG(insn1, insn2, cap, cfg, ...)	\

	alternative_insn insn1, insn2, cap, IS_ENABLED(cfg)





#endif  /*  __ASSEMBLY__  */



/*

 * Usage: asm(ALTERNATIVE(oldinstr, newinstr, feature));

 *

 * Usage: asm(ALTERNATIVE(oldinstr, newinstr, feature, CONFIG_FOO));

 * N.B. If CONFIG_FOO is specified, but not selected, the whole block

 *      will be omitted, including oldinstr.

 */

#define ALTERNATIVE(oldinstr, newinstr, ...)   \

	_ALTERNATIVE_CFG(oldinstr, newinstr, __VA_ARGS__, 1)



#endif /* __ASM_ALTERNATIVE_H */