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Commit a4eb2865 authored by Elaine Zhang's avatar Elaine Zhang Committed by Heiko Stuebner
Browse files

clk: rockchip: fix up rk3128 pvtm and mipi_24m gate regs error 



A copy-paste error made them use the wrong bits in the register.

Signed-off-by: default avatarElaine Zhang <zhangqing@rock-chips.com>
Signed-off-by: default avatarHeiko Stuebner <heiko@sntech.de>
parent e8620acc

drivers/clk/rockchip/clk-rk3128.c

+4 −4
Original line number Diff line number Diff line
@@ -315,13 +315,13 @@ static struct rockchip_clk_branch common_clk_branches[] __initdata = { 
			RK2928_CLKGATE_CON(10), 8, GFLAGS),



	GATE(SCLK_PVTM_CORE, "clk_pvtm_core", "xin24m", 0,

			RK2928_CLKGATE_CON(10), 8, GFLAGS),

			RK2928_CLKGATE_CON(10), 0, GFLAGS),

	GATE(SCLK_PVTM_GPU, "clk_pvtm_gpu", "xin24m", 0,

			RK2928_CLKGATE_CON(10), 8, GFLAGS),

			RK2928_CLKGATE_CON(10), 1, GFLAGS),

	GATE(SCLK_PVTM_FUNC, "clk_pvtm_func", "xin24m", 0,

			RK2928_CLKGATE_CON(10), 8, GFLAGS),

			RK2928_CLKGATE_CON(10), 2, GFLAGS),

	GATE(SCLK_MIPI_24M, "clk_mipi_24m", "xin24m", CLK_IGNORE_UNUSED,

			RK2928_CLKGATE_CON(10), 8, GFLAGS),

			RK2928_CLKGATE_CON(2), 15, GFLAGS),



	COMPOSITE(SCLK_SDMMC, "sclk_sdmmc0", mux_mmc_src_p, 0,

			RK2928_CLKSEL_CON(11), 6, 2, MFLAGS, 0, 6, DFLAGS,