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Commit a4a2954f authored by Sujith Manoharan's avatar Sujith Manoharan Committed by John W. Linville
Browse files

ath9k_hw: Add AR9565 HW support 



Various parts of the code require AR9565 checks,
this patch adds them.

Signed-off-by: default avatarSujith Manoharan <c_manoha@qca.qualcomm.com>
Signed-off-by: default avatarJohn W. Linville <linville@tuxdriver.com>
parent aaa53ee9

drivers/net/wireless/ath/ath9k/ani.c

+1 −1
Original line number Original line Diff line number Diff line
@@ -237,7 +237,7 @@ static void ath9k_hw_set_cck_nil(struct ath_hw *ah, u_int8_t immunityLevel, 
				     entry_cck->fir_step_level);

				     entry_cck->fir_step_level);





	/* Skip MRC CCK for pre AR9003 families */

	/* Skip MRC CCK for pre AR9003 families */

	if (!AR_SREV_9300_20_OR_LATER(ah) || AR_SREV_9485(ah))

	if (!AR_SREV_9300_20_OR_LATER(ah) || AR_SREV_9485(ah) || AR_SREV_9565(ah))

		return;

		return;





	if (aniState->mrcCCK != entry_cck->mrc_cck_on)

	if (aniState->mrcCCK != entry_cck->mrc_cck_on)

drivers/net/wireless/ath/ath9k/ar9003_eeprom.c

+5 −5
Original line number Original line Diff line number Diff line
@@ -3520,7 +3520,7 @@ static void ar9003_hw_xpa_bias_level_apply(struct ath_hw *ah, bool is2ghz) 




	if (AR_SREV_9485(ah) || AR_SREV_9330(ah) || AR_SREV_9340(ah))

	if (AR_SREV_9485(ah) || AR_SREV_9330(ah) || AR_SREV_9340(ah))

		REG_RMW_FIELD(ah, AR_CH0_TOP2, AR_CH0_TOP2_XPABIASLVL, bias);

		REG_RMW_FIELD(ah, AR_CH0_TOP2, AR_CH0_TOP2_XPABIASLVL, bias);

	else if (AR_SREV_9462(ah) || AR_SREV_9550(ah))

	else if (AR_SREV_9462(ah) || AR_SREV_9550(ah) || AR_SREV_9565(ah))

		REG_RMW_FIELD(ah, AR_CH0_TOP, AR_CH0_TOP_XPABIASLVL, bias);

		REG_RMW_FIELD(ah, AR_CH0_TOP, AR_CH0_TOP_XPABIASLVL, bias);

	else {

	else {

		REG_RMW_FIELD(ah, AR_CH0_TOP, AR_CH0_TOP_XPABIASLVL, bias);

		REG_RMW_FIELD(ah, AR_CH0_TOP, AR_CH0_TOP_XPABIASLVL, bias);
@@ -3568,7 +3568,7 @@ static void ar9003_hw_ant_ctrl_apply(struct ath_hw *ah, bool is2ghz) 




	u32 value = ar9003_hw_ant_ctrl_common_get(ah, is2ghz);

	u32 value = ar9003_hw_ant_ctrl_common_get(ah, is2ghz);





	if (AR_SREV_9462(ah)) {

	if (AR_SREV_9462(ah) || AR_SREV_9565(ah)) {

		REG_RMW_FIELD(ah, AR_PHY_SWITCH_COM,

		REG_RMW_FIELD(ah, AR_PHY_SWITCH_COM,

				AR_SWITCH_TABLE_COM_AR9462_ALL, value);

				AR_SWITCH_TABLE_COM_AR9462_ALL, value);

	} else if (AR_SREV_9550(ah)) {

	} else if (AR_SREV_9550(ah)) {
@@ -3612,7 +3612,7 @@ static void ar9003_hw_ant_ctrl_apply(struct ath_hw *ah, bool is2ghz) 
		}

		}

	}

	}





	if (AR_SREV_9330(ah) || AR_SREV_9485(ah)) {

	if (AR_SREV_9330(ah) || AR_SREV_9485(ah) || AR_SREV_9565(ah)) {

		value = ath9k_hw_ar9300_get_eeprom(ah, EEP_ANT_DIV_CTL1);

		value = ath9k_hw_ar9300_get_eeprom(ah, EEP_ANT_DIV_CTL1);

		/*

		/*

		 * main_lnaconf, alt_lnaconf, main_tb, alt_tb

		 * main_lnaconf, alt_lnaconf, main_tb, alt_tb
@@ -3843,7 +3843,7 @@ void ar9003_hw_internal_regulator_apply(struct ath_hw *ah) 
			REG_WRITE(ah, AR_PHY_PMU2, reg_pmu_set);

			REG_WRITE(ah, AR_PHY_PMU2, reg_pmu_set);

			if (!is_pmu_set(ah, AR_PHY_PMU2, reg_pmu_set))

			if (!is_pmu_set(ah, AR_PHY_PMU2, reg_pmu_set))

				return;

				return;

		} else if (AR_SREV_9462(ah)) {

		} else if (AR_SREV_9462(ah) || AR_SREV_9565(ah)) {

			reg_val = le32_to_cpu(pBase->swreg);

			reg_val = le32_to_cpu(pBase->swreg);

			REG_WRITE(ah, AR_PHY_PMU1, reg_val);

			REG_WRITE(ah, AR_PHY_PMU1, reg_val);

		} else {

		} else {
@@ -3874,7 +3874,7 @@ void ar9003_hw_internal_regulator_apply(struct ath_hw *ah) 
			while (!REG_READ_FIELD(ah, AR_PHY_PMU2,

			while (!REG_READ_FIELD(ah, AR_PHY_PMU2,

						AR_PHY_PMU2_PGM))

						AR_PHY_PMU2_PGM))

				udelay(10);

				udelay(10);

		} else if (AR_SREV_9462(ah))

		} else if (AR_SREV_9462(ah) || AR_SREV_9565(ah))

			REG_RMW_FIELD(ah, AR_PHY_PMU1, AR_PHY_PMU1_PWD, 0x1);

			REG_RMW_FIELD(ah, AR_PHY_PMU1, AR_PHY_PMU1_PWD, 0x1);

		else {

		else {

			reg_val = REG_READ(ah, AR_RTC_SLEEP_CLK) |

			reg_val = REG_READ(ah, AR_RTC_SLEEP_CLK) |

drivers/net/wireless/ath/ath9k/ar9003_mac.c

+1 −1
Original line number Original line Diff line number Diff line
@@ -31,7 +31,7 @@ ar9003_set_txdesc(struct ath_hw *ah, void *ds, struct ath_tx_info *i) 
	u32 val, ctl12, ctl17;

	u32 val, ctl12, ctl17;

	u8 desc_len;

	u8 desc_len;





	desc_len = (AR_SREV_9462(ah) ? 0x18 : 0x17);

	desc_len = ((AR_SREV_9462(ah) || AR_SREV_9565(ah)) ? 0x18 : 0x17);





	val = (ATHEROS_VENDOR_ID << AR_DescId_S) |

	val = (ATHEROS_VENDOR_ID << AR_DescId_S) |

	      (1 << AR_TxRxDesc_S) |

	      (1 << AR_TxRxDesc_S) |

drivers/net/wireless/ath/ath9k/ar9003_phy.c

+5 −5
Original line number Original line Diff line number Diff line
@@ -88,7 +88,7 @@ static int ar9003_hw_set_channel(struct ath_hw *ah, struct ath9k_channel *chan) 
			channelSel = (freq * 4) / div;

			channelSel = (freq * 4) / div;

			chan_frac = (((freq * 4) % div) * 0x20000) / div;

			chan_frac = (((freq * 4) % div) * 0x20000) / div;

			channelSel = (channelSel << 17) | chan_frac;

			channelSel = (channelSel << 17) | chan_frac;

		} else if (AR_SREV_9485(ah)) {

		} else if (AR_SREV_9485(ah) || AR_SREV_9565(ah)) {

			u32 chan_frac;

			u32 chan_frac;





			/*

			/*
@@ -736,7 +736,7 @@ static int ar9003_hw_process_ini(struct ath_hw *ah, 
	if (chan->channel == 2484)

	if (chan->channel == 2484)

		ar9003_hw_prog_ini(ah, &ah->ini_japan2484, 1);

		ar9003_hw_prog_ini(ah, &ah->ini_japan2484, 1);





	if (AR_SREV_9462(ah))

	if (AR_SREV_9462(ah) || AR_SREV_9565(ah))

		REG_WRITE(ah, AR_GLB_SWREG_DISCONT_MODE,

		REG_WRITE(ah, AR_GLB_SWREG_DISCONT_MODE,

			  AR_GLB_SWREG_DISCONT_EN_BT_WLAN);

			  AR_GLB_SWREG_DISCONT_EN_BT_WLAN);
@@ -746,7 +746,7 @@ static int ar9003_hw_process_ini(struct ath_hw *ah, 
	ar9003_hw_set_chain_masks(ah, ah->rxchainmask, ah->txchainmask);

	ar9003_hw_set_chain_masks(ah, ah->rxchainmask, ah->txchainmask);

	ath9k_hw_apply_txpower(ah, chan, false);

	ath9k_hw_apply_txpower(ah, chan, false);





	if (AR_SREV_9462(ah)) {

	if (AR_SREV_9462(ah) || AR_SREV_9565(ah)) {

		if (REG_READ_FIELD(ah, AR_PHY_TX_IQCAL_CONTROL_0,

		if (REG_READ_FIELD(ah, AR_PHY_TX_IQCAL_CONTROL_0,

				   AR_PHY_TX_IQCAL_CONTROL_0_ENABLE_TXIQ_CAL))

				   AR_PHY_TX_IQCAL_CONTROL_0_ENABLE_TXIQ_CAL))

			ah->enabled_cals |= TX_IQ_CAL;

			ah->enabled_cals |= TX_IQ_CAL;
@@ -1111,7 +1111,7 @@ static void ar9003_hw_set_nf_limits(struct ath_hw *ah) 
	if (AR_SREV_9330(ah))

	if (AR_SREV_9330(ah))

		ah->nf_2g.nominal = AR_PHY_CCA_NOM_VAL_9330_2GHZ;

		ah->nf_2g.nominal = AR_PHY_CCA_NOM_VAL_9330_2GHZ;





	if (AR_SREV_9462(ah)) {

	if (AR_SREV_9462(ah) || AR_SREV_9565(ah)) {

		ah->nf_2g.min = AR_PHY_CCA_MIN_GOOD_VAL_9462_2GHZ;

		ah->nf_2g.min = AR_PHY_CCA_MIN_GOOD_VAL_9462_2GHZ;

		ah->nf_2g.nominal = AR_PHY_CCA_NOM_VAL_9462_2GHZ;

		ah->nf_2g.nominal = AR_PHY_CCA_NOM_VAL_9462_2GHZ;

		ah->nf_5g.min = AR_PHY_CCA_MIN_GOOD_VAL_9462_5GHZ;

		ah->nf_5g.min = AR_PHY_CCA_MIN_GOOD_VAL_9462_5GHZ;

drivers/net/wireless/ath/ath9k/ar9003_phy.h

+7 −7
Original line number Original line Diff line number Diff line
@@ -636,8 +636,8 @@ 
#define AR_PHY_65NM_CH0_TXRF3_CAPDIV2G_S	1

#define AR_PHY_65NM_CH0_TXRF3_CAPDIV2G_S	1





#define AR_PHY_65NM_CH0_SYNTH4      0x1608c

#define AR_PHY_65NM_CH0_SYNTH4      0x1608c

#define AR_PHY_SYNTH4_LONG_SHIFT_SELECT   (AR_SREV_9462(ah) ? 0x00000001 : 0x00000002)

#define AR_PHY_SYNTH4_LONG_SHIFT_SELECT   ((AR_SREV_9462(ah) || AR_SREV_9565(ah)) ? 0x00000001 : 0x00000002)

#define AR_PHY_SYNTH4_LONG_SHIFT_SELECT_S (AR_SREV_9462(ah) ? 0 : 1)

#define AR_PHY_SYNTH4_LONG_SHIFT_SELECT_S ((AR_SREV_9462(ah) || AR_SREV_9565(ah)) ? 0 : 1)

#define AR_PHY_65NM_CH0_SYNTH7      0x16098

#define AR_PHY_65NM_CH0_SYNTH7      0x16098

#define AR_PHY_65NM_CH0_BIAS1       0x160c0

#define AR_PHY_65NM_CH0_BIAS1       0x160c0

#define AR_PHY_65NM_CH0_BIAS2       0x160c4

#define AR_PHY_65NM_CH0_BIAS2       0x160c4
@@ -647,7 +647,7 @@ 
#define AR_PHY_65NM_CH2_RXTX4       0x1690c

#define AR_PHY_65NM_CH2_RXTX4       0x1690c





#define AR_CH0_TOP	(AR_SREV_9300(ah) ? 0x16288 : \

#define AR_CH0_TOP	(AR_SREV_9300(ah) ? 0x16288 : \

				((AR_SREV_9462(ah) ? 0x1628c : 0x16280)))

			 (((AR_SREV_9462(ah) || AR_SREV_9565(ah)) ? 0x1628c : 0x16280)))

#define AR_CH0_TOP_XPABIASLVL (AR_SREV_9550(ah) ? 0x3c0 : 0x300)

#define AR_CH0_TOP_XPABIASLVL (AR_SREV_9550(ah) ? 0x3c0 : 0x300)

#define AR_CH0_TOP_XPABIASLVL_S (AR_SREV_9550(ah) ? 6 : 8)

#define AR_CH0_TOP_XPABIASLVL_S (AR_SREV_9550(ah) ? 6 : 8)
@@ -675,7 +675,7 @@ 
#define AR_SWITCH_TABLE_ALL_S (0)

#define AR_SWITCH_TABLE_ALL_S (0)





#define AR_PHY_65NM_CH0_THERM       (AR_SREV_9300(ah) ? 0x16290 :\

#define AR_PHY_65NM_CH0_THERM       (AR_SREV_9300(ah) ? 0x16290 :\

					(AR_SREV_9462(ah) ? 0x16294 : 0x1628c))

				     ((AR_SREV_9462(ah) || AR_SREV_9565(ah)) ? 0x16294 : 0x1628c))





#define AR_PHY_65NM_CH0_THERM_LOCAL   0x80000000

#define AR_PHY_65NM_CH0_THERM_LOCAL   0x80000000

#define AR_PHY_65NM_CH0_THERM_LOCAL_S 31

#define AR_PHY_65NM_CH0_THERM_LOCAL_S 31
@@ -697,17 +697,17 @@ 
#define AR_CH0_TOP2_XPABIASLVL_S	12

#define AR_CH0_TOP2_XPABIASLVL_S	12





#define AR_CH0_XTAL		(AR_SREV_9300(ah) ? 0x16294 : \

#define AR_CH0_XTAL		(AR_SREV_9300(ah) ? 0x16294 : \

					(AR_SREV_9462(ah) ? 0x16298 : 0x16290))

				 ((AR_SREV_9462(ah) || AR_SREV_9565(ah)) ? 0x16298 : 0x16290))

#define AR_CH0_XTAL_CAPINDAC	0x7f000000

#define AR_CH0_XTAL_CAPINDAC	0x7f000000

#define AR_CH0_XTAL_CAPINDAC_S	24

#define AR_CH0_XTAL_CAPINDAC_S	24

#define AR_CH0_XTAL_CAPOUTDAC	0x00fe0000

#define AR_CH0_XTAL_CAPOUTDAC	0x00fe0000

#define AR_CH0_XTAL_CAPOUTDAC_S	17

#define AR_CH0_XTAL_CAPOUTDAC_S	17





#define AR_PHY_PMU1		(AR_SREV_9462(ah) ? 0x16340 : 0x16c40)

#define AR_PHY_PMU1		((AR_SREV_9462(ah) || AR_SREV_9565(ah)) ? 0x16340 : 0x16c40)

#define AR_PHY_PMU1_PWD		0x1

#define AR_PHY_PMU1_PWD		0x1

#define AR_PHY_PMU1_PWD_S	0

#define AR_PHY_PMU1_PWD_S	0





#define AR_PHY_PMU2		(AR_SREV_9462(ah) ? 0x16344 : 0x16c44)

#define AR_PHY_PMU2		((AR_SREV_9462(ah) || AR_SREV_9565(ah)) ? 0x16344 : 0x16c44)

#define AR_PHY_PMU2_PGM		0x00200000

#define AR_PHY_PMU2_PGM		0x00200000

#define AR_PHY_PMU2_PGM_S	21

#define AR_PHY_PMU2_PGM_S	21