ath9k_hw: Add AR9565 initvals (aaa53ee9) · Commits · e / devices / android_kernel_fairphone_FP4

drivers/net/wireless/ath/ath9k/ar9003_hw.c

+52 −5

Original line number	Original line	Diff line number	Diff line
	@@ -24,6 +24,7 @@
	#include "ar955x_1p0_initvals.h"		#include "ar955x_1p0_initvals.h"
	#include "ar9580_1p0_initvals.h"		#include "ar9580_1p0_initvals.h"
	#include "ar9462_2p0_initvals.h"		#include "ar9462_2p0_initvals.h"
			#include "ar9565_1p0_initvals.h"

	/* General hardware code for the AR9003 hadware family */		/* General hardware code for the AR9003 hadware family */

	@@ -34,14 +35,12 @@
	*/		*/
	static void ar9003_hw_init_mode_regs(struct ath_hw *ah)		static void ar9003_hw_init_mode_regs(struct ath_hw *ah)
	{		{
	#define PCIE_PLL_ON_CREQ_DIS_L1_2P0 \
	ar9462_pciephy_pll_on_clkreq_disable_L1_2p0

	#define AR9462_BB_CTX_COEFJ(x) \		#define AR9462_BB_CTX_COEFJ(x) \
	ar9462_##x##_baseband_core_txfir_coeff_japan_2484		ar9462_##x##_baseband_core_txfir_coeff_japan_2484

	#define AR9462_BBC_TXIFR_COEFFJ \		#define AR9462_BBC_TXIFR_COEFFJ \
	ar9462_2p0_baseband_core_txfir_coeff_japan_2484		ar9462_2p0_baseband_core_txfir_coeff_japan_2484

	if (AR_SREV_9330_11(ah)) {		if (AR_SREV_9330_11(ah)) {
	/* mac */		/* mac */
	INIT_INI_ARRAY(&ah->iniMac[ATH_INI_CORE],		INIT_INI_ARRAY(&ah->iniMac[ATH_INI_CORE],
	@@ -220,10 +219,10 @@ static void ar9003_hw_init_mode_regs(struct ath_hw *ah)

	/* Awake -> Sleep Setting */		/* Awake -> Sleep Setting */
	INIT_INI_ARRAY(&ah->iniPcieSerdes,		INIT_INI_ARRAY(&ah->iniPcieSerdes,
	PCIE_PLL_ON_CREQ_DIS_L1_2P0);		ar9462_pciephy_pll_on_clkreq_disable_L1_2p0);
	/* Sleep -> Awake Setting */		/* Sleep -> Awake Setting */
	INIT_INI_ARRAY(&ah->iniPcieSerdesLowPower,		INIT_INI_ARRAY(&ah->iniPcieSerdesLowPower,
	PCIE_PLL_ON_CREQ_DIS_L1_2P0);		ar9462_pciephy_pll_on_clkreq_disable_L1_2p0);

	/* Fast clock modal settings */		/* Fast clock modal settings */
	INIT_INI_ARRAY(&ah->iniModesFastClock,		INIT_INI_ARRAY(&ah->iniModesFastClock,
	@@ -302,6 +301,39 @@ static void ar9003_hw_init_mode_regs(struct ath_hw *ah)

	INIT_INI_ARRAY(&ah->iniModesFastClock,		INIT_INI_ARRAY(&ah->iniModesFastClock,
	ar9580_1p0_modes_fast_clock);		ar9580_1p0_modes_fast_clock);
			} else if (AR_SREV_9565(ah)) {
			INIT_INI_ARRAY(&ah->iniMac[ATH_INI_CORE],
			ar9565_1p0_mac_core);
			INIT_INI_ARRAY(&ah->iniMac[ATH_INI_POST],
			ar9565_1p0_mac_postamble);

			INIT_INI_ARRAY(&ah->iniBB[ATH_INI_CORE],
			ar9565_1p0_baseband_core);
			INIT_INI_ARRAY(&ah->iniBB[ATH_INI_POST],
			ar9565_1p0_baseband_postamble);

			INIT_INI_ARRAY(&ah->iniRadio[ATH_INI_CORE],
			ar9565_1p0_radio_core);
			INIT_INI_ARRAY(&ah->iniRadio[ATH_INI_POST],
			ar9565_1p0_radio_postamble);

			INIT_INI_ARRAY(&ah->iniSOC[ATH_INI_PRE],
			ar9565_1p0_soc_preamble);
			INIT_INI_ARRAY(&ah->iniSOC[ATH_INI_POST],
			ar9565_1p0_soc_postamble);

			INIT_INI_ARRAY(&ah->iniModesRxGain,
			ar9565_1p0_Common_rx_gain_table);
			INIT_INI_ARRAY(&ah->iniModesTxGain,
			ar9565_1p0_Modes_lowest_ob_db_tx_gain_table);

			INIT_INI_ARRAY(&ah->iniPcieSerdes,
			ar9565_1p0_pciephy_pll_on_clkreq_disable_L1);
			INIT_INI_ARRAY(&ah->iniPcieSerdesLowPower,
			ar9565_1p0_pciephy_pll_on_clkreq_disable_L1);

			INIT_INI_ARRAY(&ah->iniModesFastClock,
			ar9565_1p0_modes_fast_clock);
	} else {		} else {
	/* mac */		/* mac */
	INIT_INI_ARRAY(&ah->iniMac[ATH_INI_CORE],		INIT_INI_ARRAY(&ah->iniMac[ATH_INI_CORE],
	@@ -374,6 +406,9 @@ static void ar9003_tx_gain_table_mode0(struct ath_hw *ah)
	else if (AR_SREV_9462_20(ah))		else if (AR_SREV_9462_20(ah))
	INIT_INI_ARRAY(&ah->iniModesTxGain,		INIT_INI_ARRAY(&ah->iniModesTxGain,
	ar9462_modes_low_ob_db_tx_gain_table_2p0);		ar9462_modes_low_ob_db_tx_gain_table_2p0);
			else if (AR_SREV_9565(ah))
			INIT_INI_ARRAY(&ah->iniModesTxGain,
			ar9565_1p0_modes_low_ob_db_tx_gain_table);
	else		else
	INIT_INI_ARRAY(&ah->iniModesTxGain,		INIT_INI_ARRAY(&ah->iniModesTxGain,
	ar9300Modes_lowest_ob_db_tx_gain_table_2p2);		ar9300Modes_lowest_ob_db_tx_gain_table_2p2);
	@@ -402,6 +437,9 @@ static void ar9003_tx_gain_table_mode1(struct ath_hw *ah)
	else if (AR_SREV_9462_20(ah))		else if (AR_SREV_9462_20(ah))
	INIT_INI_ARRAY(&ah->iniModesTxGain,		INIT_INI_ARRAY(&ah->iniModesTxGain,
	ar9462_modes_high_ob_db_tx_gain_table_2p0);		ar9462_modes_high_ob_db_tx_gain_table_2p0);
			else if (AR_SREV_9565(ah))
			INIT_INI_ARRAY(&ah->iniModesTxGain,
			ar9565_1p0_modes_high_ob_db_tx_gain_table);
	else		else
	INIT_INI_ARRAY(&ah->iniModesTxGain,		INIT_INI_ARRAY(&ah->iniModesTxGain,
	ar9300Modes_high_ob_db_tx_gain_table_2p2);		ar9300Modes_high_ob_db_tx_gain_table_2p2);
	@@ -424,6 +462,9 @@ static void ar9003_tx_gain_table_mode2(struct ath_hw *ah)
	else if (AR_SREV_9580(ah))		else if (AR_SREV_9580(ah))
	INIT_INI_ARRAY(&ah->iniModesTxGain,		INIT_INI_ARRAY(&ah->iniModesTxGain,
	ar9580_1p0_low_ob_db_tx_gain_table);		ar9580_1p0_low_ob_db_tx_gain_table);
			else if (AR_SREV_9565(ah))
			INIT_INI_ARRAY(&ah->iniModesTxGain,
			ar9565_1p0_modes_low_ob_db_tx_gain_table);
	else		else
	INIT_INI_ARRAY(&ah->iniModesTxGain,		INIT_INI_ARRAY(&ah->iniModesTxGain,
	ar9300Modes_low_ob_db_tx_gain_table_2p2);		ar9300Modes_low_ob_db_tx_gain_table_2p2);
	@@ -446,6 +487,9 @@ static void ar9003_tx_gain_table_mode3(struct ath_hw *ah)
	else if (AR_SREV_9580(ah))		else if (AR_SREV_9580(ah))
	INIT_INI_ARRAY(&ah->iniModesTxGain,		INIT_INI_ARRAY(&ah->iniModesTxGain,
	ar9580_1p0_high_power_tx_gain_table);		ar9580_1p0_high_power_tx_gain_table);
			else if (AR_SREV_9565(ah))
			INIT_INI_ARRAY(&ah->iniModesTxGain,
			ar9565_1p0_modes_high_power_tx_gain_table);
	else		else
	INIT_INI_ARRAY(&ah->iniModesTxGain,		INIT_INI_ARRAY(&ah->iniModesTxGain,
	ar9300Modes_high_power_tx_gain_table_2p2);		ar9300Modes_high_power_tx_gain_table_2p2);
	@@ -538,6 +582,9 @@ static void ar9003_rx_gain_table_mode1(struct ath_hw *ah)
	} else if (AR_SREV_9580(ah))		} else if (AR_SREV_9580(ah))
	INIT_INI_ARRAY(&ah->iniModesRxGain,		INIT_INI_ARRAY(&ah->iniModesRxGain,
	ar9580_1p0_wo_xlna_rx_gain_table);		ar9580_1p0_wo_xlna_rx_gain_table);
			else if (AR_SREV_9565(ah))
			INIT_INI_ARRAY(&ah->iniModesRxGain,
			ar9565_1p0_common_wo_xlna_rx_gain_table);
	else		else
	INIT_INI_ARRAY(&ah->iniModesRxGain,		INIT_INI_ARRAY(&ah->iniModesRxGain,
	ar9300Common_wo_xlna_rx_gain_table_2p2);		ar9300Common_wo_xlna_rx_gain_table_2p2);

drivers/net/wireless/ath/ath9k/ar9003_phy.c

+6 −3

Original line number	Original line	Diff line number	Diff line
	@@ -1312,9 +1312,9 @@ static int ar9003_hw_fast_chan_change(struct ath_hw *ah,
	ar9003_hw_prog_ini(ah, &ah->iniMac[ATH_INI_POST], modesIndex);		ar9003_hw_prog_ini(ah, &ah->iniMac[ATH_INI_POST], modesIndex);
	ar9003_hw_prog_ini(ah, &ah->iniBB[ATH_INI_POST], modesIndex);		ar9003_hw_prog_ini(ah, &ah->iniBB[ATH_INI_POST], modesIndex);
	ar9003_hw_prog_ini(ah, &ah->iniRadio[ATH_INI_POST], modesIndex);		ar9003_hw_prog_ini(ah, &ah->iniRadio[ATH_INI_POST], modesIndex);

	if (AR_SREV_9462_20(ah))		if (AR_SREV_9462_20(ah))
	ar9003_hw_prog_ini(ah,		ar9003_hw_prog_ini(ah, &ah->ini_radio_post_sys2ant,
	&ah->ini_radio_post_sys2ant,
	modesIndex);		modesIndex);

	REG_WRITE_ARRAY(&ah->iniModesTxGain, modesIndex, regWrites);		REG_WRITE_ARRAY(&ah->iniModesTxGain, modesIndex, regWrites);
	@@ -1326,6 +1326,9 @@ static int ar9003_hw_fast_chan_change(struct ath_hw *ah,
	if (IS_CHAN_A_FAST_CLOCK(ah, chan))		if (IS_CHAN_A_FAST_CLOCK(ah, chan))
	REG_WRITE_ARRAY(&ah->iniModesFastClock, modesIndex, regWrites);		REG_WRITE_ARRAY(&ah->iniModesFastClock, modesIndex, regWrites);

			if (AR_SREV_9565(ah))
			REG_WRITE_ARRAY(&ah->iniModesFastClock, 1, regWrites);

	REG_WRITE_ARRAY(&ah->iniAdditional, 1, regWrites);		REG_WRITE_ARRAY(&ah->iniAdditional, 1, regWrites);

	ah->modes_index = modesIndex;		ah->modes_index = modesIndex;

drivers/net/wireless/ath/ath9k/ar9565_1p0_initvals.h

0 → 100644

+1233 −0

File added.

Preview size limit exceeded, changes collapsed.