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Commit a3692020 authored by Ralf Baechle's avatar Ralf Baechle
Browse files

[MIPS] Enable support for the userlocal hardware register 



Which will cut down the cost of RDHWR $29 which is used to obtain the
TLS pointer and so far being emulated in software down to a single cycle
operation.

Signed-off-by: default avatarRalf Baechle <ralf@linux-mips.org>
parent d223a861

arch/mips/kernel/cpu-probe.c

+2 −0
Original line number Original line Diff line number Diff line
@@ -588,6 +588,8 @@ static inline unsigned int decode_config3(struct cpuinfo_mips *c) 
		c->options |= MIPS_CPU_VEIC;

		c->options |= MIPS_CPU_VEIC;

	if (config3 & MIPS_CONF3_MT)

	if (config3 & MIPS_CONF3_MT)

	        c->ases |= MIPS_ASE_MIPSMT;

	        c->ases |= MIPS_ASE_MIPSMT;

	if (config3 & MIPS_CONF3_ULRI)

		c->options |= MIPS_CPU_ULRI;





	return config3 & MIPS_CONF_M;

	return config3 & MIPS_CONF_M;

}

}

arch/mips/kernel/syscall.c

+2 −3
Original line number Original line Diff line number Diff line
@@ -272,9 +272,8 @@ asmlinkage int sys_set_thread_area(unsigned long addr) 
	struct thread_info *ti = task_thread_info(current);

	struct thread_info *ti = task_thread_info(current);





	ti->tp_value = addr;

	ti->tp_value = addr;



	if (cpu_has_userlocal)

	/* If some future MIPS implementation has this register in hardware,

		write_c0_userlocal(addr);

	 * we will need to update it here (and in context switches).  */





	return 0;

	return 0;

}

}

arch/mips/kernel/traps.c

+8 −1
Original line number Original line Diff line number Diff line
@@ -1341,7 +1341,14 @@ void __init per_cpu_trap_init(void) 
		set_c0_status(ST0_MX);

		set_c0_status(ST0_MX);





#ifdef CONFIG_CPU_MIPSR2

#ifdef CONFIG_CPU_MIPSR2

	write_c0_hwrena (0x0000000f); /* Allow rdhwr to all registers */

	if (cpu_has_mips_r2) {

		unsigned int enable = 0x0000000f;



		if (cpu_has_userlocal)

			enable |= (1 << 29);



		write_c0_hwrena(enable);

	}

#endif

#endif





#ifdef CONFIG_MIPS_MT_SMTC

#ifdef CONFIG_MIPS_MT_SMTC

include/asm-mips/cpu-features.h

+4 −0
Original line number Original line Diff line number Diff line
@@ -150,6 +150,10 @@ 
#define cpu_has_mipsmt		(cpu_data[0].ases & MIPS_ASE_MIPSMT)

#define cpu_has_mipsmt		(cpu_data[0].ases & MIPS_ASE_MIPSMT)

#endif

#endif





#ifndef cpu_has_userlocal

#define cpu_has_userlocal	(cpu_data[0].options & MIPS_CPU_ULRI)

#endif



#ifdef CONFIG_32BIT

#ifdef CONFIG_32BIT

# ifndef cpu_has_nofpuex

# ifndef cpu_has_nofpuex

# define cpu_has_nofpuex	(cpu_data[0].options & MIPS_CPU_NOFPUEX)

# define cpu_has_nofpuex	(cpu_data[0].options & MIPS_CPU_NOFPUEX)

include/asm-mips/cpu.h

+1 −0
Original line number Original line Diff line number Diff line
@@ -257,6 +257,7 @@ 
#define MIPS_CPU_PREFETCH	0x00080000 /* CPU has usable prefetch */

#define MIPS_CPU_PREFETCH	0x00080000 /* CPU has usable prefetch */

#define MIPS_CPU_VINT		0x00100000 /* CPU supports MIPSR2 vectored interrupts */

#define MIPS_CPU_VINT		0x00100000 /* CPU supports MIPSR2 vectored interrupts */

#define MIPS_CPU_VEIC		0x00200000 /* CPU supports MIPSR2 external interrupt controller mode */

#define MIPS_CPU_VEIC		0x00200000 /* CPU supports MIPSR2 external interrupt controller mode */

#define MIPS_CPU_ULRI		0x00400000 /* CPU has ULRI feature */





/*

/*

 * CPU ASE encodings

 * CPU ASE encodings