[MIPS] FP affinity: Coding style cleanups (d223a861) · Commits · e / devices / android_kernel_fairphone_FP4

arch/mips/kernel/mips-mt.c

+22 −18

Original line number	Diff line number	Diff line
		@@ -200,12 +200,16 @@ void mips_mt_regdump(unsigned long mvpctl)
		settc(tc);
		if ((read_tc_c0_tcbind() & TCBIND_CURVPE) == i) {
		printk(" VPE %d\n", i);
		printk(" VPEControl : %08lx\n", read_vpe_c0_vpecontrol());
		printk(" VPEConf0 : %08lx\n", read_vpe_c0_vpeconf0());
		printk(" VPEControl : %08lx\n",
		read_vpe_c0_vpecontrol());
		printk(" VPEConf0 : %08lx\n",
		read_vpe_c0_vpeconf0());
		printk(" VPE%d.Status : %08lx\n",
		i, read_vpe_c0_status());
		printk(" VPE%d.EPC : %08lx\n", i, read_vpe_c0_epc());
		printk(" VPE%d.Cause : %08lx\n", i, read_vpe_c0_cause());
		printk(" VPE%d.EPC : %08lx\n",
		i, read_vpe_c0_epc());
		printk(" VPE%d.Cause : %08lx\n",
		i, read_vpe_c0_cause());
		printk(" VPE%d.Config7 : %08lx\n",
		i, read_vpe_c0_config7());
		break; /* Next VPE */

arch/mips/kernel/traps.c

+29 −30

Original line number	Diff line number	Diff line
		@@ -752,6 +752,33 @@ asmlinkage void do_ri(struct pt_regs *regs)
		force_sig(SIGILL, current);
		}

		/*
		* MIPS MT processors may have fewer FPU contexts than CPU threads. If we've
		* emulated more than some threshold number of instructions, force migration to
		* a "CPU" that has FP support.
		*/
		static void mt_ase_fp_affinity(void)
		{
		#ifdef CONFIG_MIPS_MT_FPAFF
		if (mt_fpemul_threshold > 0 &&
		((current->thread.emulated_fp++ > mt_fpemul_threshold))) {
		/*
		* If there's no FPU present, or if the application has already
		* restricted the allowed set to exclude any CPUs with FPUs,
		* we'll skip the procedure.
		*/
		if (cpus_intersects(current->cpus_allowed, mt_fpu_cpumask)) {
		cpumask_t tmask;

		cpus_and(tmask, current->thread.user_cpus_allowed,
		mt_fpu_cpumask);
		set_cpus_allowed(current, tmask);
		current->thread.mflags \|= MF_FPUBOUND;
		}
		}
		#endif /* CONFIG_MIPS_MT_FPAFF */
		}

		asmlinkage void do_cpu(struct pt_regs *regs)
		{
		unsigned int cpid;
		@@ -785,36 +812,8 @@ asmlinkage void do_cpu(struct pt_regs *regs)
		&current->thread.fpu, 0);
		if (sig)
		force_sig(sig, current);
		#ifdef CONFIG_MIPS_MT_FPAFF
		else {
		/*
		* MIPS MT processors may have fewer FPU contexts
		* than CPU threads. If we've emulated more than
		* some threshold number of instructions, force
		* migration to a "CPU" that has FP support.
		*/
		if(mt_fpemul_threshold > 0
		&& ((current->thread.emulated_fp++
		> mt_fpemul_threshold))) {
		/*
		* If there's no FPU present, or if the
		* application has already restricted
		* the allowed set to exclude any CPUs
		* with FPUs, we'll skip the procedure.
		*/
		if (cpus_intersects(current->cpus_allowed,
		mt_fpu_cpumask)) {
		cpumask_t tmask;

		cpus_and(tmask,
		current->thread.user_cpus_allowed,
		mt_fpu_cpumask);
		set_cpus_allowed(current, tmask);
		current->thread.mflags \|= MF_FPUBOUND;
		}
		}
		}
		#endif /* CONFIG_MIPS_MT_FPAFF */
		else
		mt_ase_fp_affinity();
		}

		return;

include/asm-mips/system.h

+5 −7

Original line number	Diff line number	Diff line
		@@ -44,7 +44,7 @@ struct task_struct;
		* different thread.
		*/

		#define switch_to(prev,next,last) \
		#define __mips_mt_fpaff_switch_to(prev) \
		do { \
		if (cpu_has_fpu && \
		(prev->thread.mflags & MF_FPUBOUND) && \
		@@ -52,24 +52,22 @@ do { \
		prev->thread.mflags &= ~MF_FPUBOUND; \
		prev->cpus_allowed = prev->thread.user_cpus_allowed; \
		} \
		if (cpu_has_dsp) \
		__save_dsp(prev); \
		next->thread.emulated_fp = 0; \
		(last) = resume(prev, next, task_thread_info(next)); \
		if (cpu_has_dsp) \
		__restore_dsp(current); \
		} while(0)

		#else
		#define __mips_mt_fpaff_switch_to(prev) do { (prev); } while (0)
		#endif

		#define switch_to(prev,next,last) \
		do { \
		__mips_mt_fpaff_switch_to(prev); \
		if (cpu_has_dsp) \
		__save_dsp(prev); \
		(last) = resume(prev, next, task_thread_info(next)); \
		if (cpu_has_dsp) \
		__restore_dsp(current); \
		} while(0)
		#endif

		/*
		* On SMP systems, when the scheduler does migration-cost autodetection,