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Commit a14083fe authored by Martin Blumenstingl's avatar Martin Blumenstingl Committed by Greg Kroah-Hartman
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drm: meson: venc: cvbs: fix CVBS mode matching 



commit 43cb86799ff03e9819c07f37f72f80f8246ad7ed upstream.

With commit 222ec161 ("drm: Add aspect ratio parsing in DRM
layer") the drm core started honoring the picture_aspect_ratio field
when comparing two drm_display_modes. Prior to that it was ignored.
When the CVBS encoder driver was initially submitted there was no aspect
ratio check.

Switch from drm_mode_equal() to drm_mode_match() without
DRM_MODE_MATCH_ASPECT_RATIO to fix "kmscube" and X.org output using the
CVBS connector. When (for example) kmscube sets the output mode when
using the CVBS connector it passes HDMI_PICTURE_ASPECT_NONE, making the
drm_mode_equal() fail as it include the aspect ratio.

Prior to this patch kmscube reported:
  failed to set mode: Invalid argument

The CVBS mode checking in the sun4i (drivers/gpu/drm/sun4i/sun4i_tv.c
sun4i_tv_mode_to_drm_mode) and ZTE (drivers/gpu/drm/zte/zx_tvenc.c
tvenc_mode_{pal,ntsc}) drivers don't set the "picture_aspect_ratio" at
all. The Meson VPU driver does not rely on the aspect ratio for the CVBS
output so we can safely decouple it from the hdmi_picture_aspect
setting.

Cc: <stable@vger.kernel.org>
Fixes: 222ec161 ("drm: Add aspect ratio parsing in DRM layer")
Fixes: bbbe775e ("drm: Add support for Amlogic Meson Graphic Controller")
Signed-off-by: default avatarMartin Blumenstingl <martin.blumenstingl@googlemail.com>
Acked-by: default avatarNeil Armstrong <narmstrong@baylibre.com>
[narmstrong: squashed with drm: meson: venc: cvbs: deduplicate the meson_cvbs_mode lookup code]
Signed-off-by: default avatarNeil Armstrong <narmstrong@baylibre.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20191208171832.1064772-3-martin.blumenstingl@googlemail.com


Signed-off-by: default avatarGreg Kroah-Hartman <gregkh@linuxfoundation.org>
parent 009484c9

drivers/gpu/drm/meson/meson_venc_cvbs.c

+27 −21
Original line number Diff line number Diff line
@@ -75,6 +75,25 @@ struct meson_cvbs_mode meson_cvbs_modes[MESON_CVBS_MODES_COUNT] = { 
	},

};



static const struct meson_cvbs_mode *

meson_cvbs_get_mode(const struct drm_display_mode *req_mode)

{

	int i;



	for (i = 0; i < MESON_CVBS_MODES_COUNT; ++i) {

		struct meson_cvbs_mode *meson_mode = &meson_cvbs_modes[i];



		if (drm_mode_match(req_mode, &meson_mode->mode,

				   DRM_MODE_MATCH_TIMINGS |

				   DRM_MODE_MATCH_CLOCK |

				   DRM_MODE_MATCH_FLAGS |

				   DRM_MODE_MATCH_3D_FLAGS))

			return meson_mode;

	}



	return NULL;

}



/* Connector */



static void meson_cvbs_connector_destroy(struct drm_connector *connector)
@@ -147,14 +166,8 @@ static int meson_venc_cvbs_encoder_atomic_check(struct drm_encoder *encoder, 
					struct drm_crtc_state *crtc_state,

					struct drm_connector_state *conn_state)

{

	int i;



	for (i = 0; i < MESON_CVBS_MODES_COUNT; ++i) {

		struct meson_cvbs_mode *meson_mode = &meson_cvbs_modes[i];



		if (drm_mode_equal(&crtc_state->mode, &meson_mode->mode))

	if (meson_cvbs_get_mode(&crtc_state->mode))

		return 0;

	}



	return -EINVAL;

}
@@ -192,24 +205,17 @@ static void meson_venc_cvbs_encoder_mode_set(struct drm_encoder *encoder, 
				   struct drm_display_mode *mode,

				   struct drm_display_mode *adjusted_mode)

{

	const struct meson_cvbs_mode *meson_mode = meson_cvbs_get_mode(mode);

	struct meson_venc_cvbs *meson_venc_cvbs =

					encoder_to_meson_venc_cvbs(encoder);

	struct meson_drm *priv = meson_venc_cvbs->priv;

	int i;



	for (i = 0; i < MESON_CVBS_MODES_COUNT; ++i) {

		struct meson_cvbs_mode *meson_mode = &meson_cvbs_modes[i];



		if (drm_mode_equal(mode, &meson_mode->mode)) {

			meson_venci_cvbs_mode_set(priv,

						  meson_mode->enci);

	if (meson_mode) {

		meson_venci_cvbs_mode_set(priv, meson_mode->enci);



		/* Setup 27MHz vclk2 for ENCI and VDAC */

			meson_vclk_setup(priv, MESON_VCLK_TARGET_CVBS,

					 MESON_VCLK_CVBS, MESON_VCLK_CVBS,

					 MESON_VCLK_CVBS, true);

			break;

		}

		meson_vclk_setup(priv, MESON_VCLK_TARGET_CVBS, MESON_VCLK_CVBS,

				 MESON_VCLK_CVBS, MESON_VCLK_CVBS, true);

	}

}