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Commit bbbe775e authored by Neil Armstrong's avatar Neil Armstrong
Browse files

drm: Add support for Amlogic Meson Graphic Controller 



The Amlogic Meson Display controller is composed of several components :

DMC|---------------VPU (Video Processing Unit)----------------|------HHI------|
   | vd1   _______     _____________    _________________     |               |
D  |-------|      |----|            |   |                |    |   HDMI PLL    |
D  | vd2   | VIU  |    | Video Post |   | Video Encoders |<---|-----VCLK      |
R  |-------|      |----| Processing |   |                |    |               |
   | osd2  |      |    |            |---| Enci ----------|----|-----VDAC------|
R  |-------| CSC  |----| Scalers    |   | Encp ----------|----|----HDMI-TX----|
A  | osd1  |      |    | Blenders   |   | Encl ----------|----|---------------|
M  |-------|______|----|____________|   |________________|    |               |
___|__________________________________________________________|_______________|

VIU: Video Input Unit
---------------------

The Video Input Unit is in charge of the pixel scanout from the DDR memory.
It fetches the frames addresses, stride and parameters from the "Canvas" memory.
This part is also in charge of the CSC (Colorspace Conversion).
It can handle 2 OSD Planes and 2 Video Planes.

VPP: Video Post Processing
--------------------------

The Video Post Processing is in charge of the scaling and blending of the
various planes into a single pixel stream.
There is a special "pre-blending" used by the video planes with a dedicated
scaler and a "post-blending" to merge with the OSD Planes.
The OSD planes also have a dedicated scaler for one of the OSD.

VENC: Video Encoders
--------------------

The VENC is composed of the multiple pixel encoders :
 - ENCI : Interlace Video encoder for CVBS and Interlace HDMI
 - ENCP : Progressive Video Encoder for HDMI
 - ENCL : LCD LVDS Encoder
The VENC Unit gets a Pixel Clocks (VCLK) from a dedicated HDMI PLL and clock
tree and provides the scanout clock to the VPP and VIU.
The ENCI is connected to a single VDAC for Composite Output.
The ENCI and ENCP are connected to an on-chip HDMI Transceiver.

This driver is a DRM/KMS driver using the following DRM components :
 - GEM-CMA
 - PRIME-CMA
 - Atomic Modesetting
 - FBDev-CMA

For the following SoCs :
 - GXBB Family (S905)
 - GXL Family (S905X, S905D)
 - GXM Family (S912)

The current driver only supports the CVBS PAL/NTSC output modes, but the
CRTC/Planes management should support bigger modes.
But Advanced Colorspace Conversion, Scaling and HDMI Modes will be added in
a second time.

The Device Tree bindings makes use of the endpoints video interface definitions
to connect to the optional CVBS and in the future the HDMI Connector nodes.

HDMI Support is planned for a next release.

Acked-by: default avatarDaniel Vetter <daniel.vetter@ffwll.ch>
Signed-off-by: default avatarNeil Armstrong <narmstrong@baylibre.com>
parent bc33b0ca

drivers/gpu/drm/Kconfig

+2 −0
Original line number Diff line number Diff line
@@ -223,6 +223,8 @@ source "drivers/gpu/drm/hisilicon/Kconfig" 


source "drivers/gpu/drm/mediatek/Kconfig"



source "drivers/gpu/drm/meson/Kconfig"



# Keep legacy drivers last



menuconfig DRM_LEGACY

drivers/gpu/drm/Makefile

+1 −0
Original line number Diff line number Diff line
@@ -79,6 +79,7 @@ obj-$(CONFIG_DRM_TEGRA) += tegra/ 
obj-$(CONFIG_DRM_STI) += sti/

obj-$(CONFIG_DRM_IMX) += imx/

obj-$(CONFIG_DRM_MEDIATEK) += mediatek/

obj-$(CONFIG_DRM_MESON)	+= meson/

obj-y			+= i2c/

obj-y			+= panel/

obj-y			+= bridge/

drivers/gpu/drm/meson/Kconfig

0 → 100644
+9 −0
Original line number Diff line number Diff line 
config DRM_MESON

	tristate "DRM Support for Amlogic Meson Display Controller"

	depends on DRM && OF && (ARM || ARM64)

	depends on ARCH_MESON || COMPILE_TEST

	select DRM_KMS_HELPER

	select DRM_KMS_CMA_HELPER

	select DRM_GEM_CMA_HELPER

	select VIDEOMODE_HELPERS

	select REGMAP_MMIO

drivers/gpu/drm/meson/Makefile

0 → 100644
+4 −0
Original line number Diff line number Diff line 
meson-y := meson_drv.o meson_plane.o meson_crtc.o meson_venc_cvbs.o

meson-y += meson_viu.o meson_vpp.o meson_venc.o meson_vclk.o meson_canvas.o



obj-$(CONFIG_DRM_MESON) += meson.o

drivers/gpu/drm/meson/meson_canvas.c

0 → 100644
+68 −0
Original line number Diff line number Diff line 
/*

 * Copyright (C) 2016 BayLibre, SAS

 * Author: Neil Armstrong <narmstrong@baylibre.com>

 * Copyright (C) 2015 Amlogic, Inc. All rights reserved.

 * Copyright (C) 2014 Endless Mobile

 *

 * This program is free software; you can redistribute it and/or

 * modify it under the terms of the GNU General Public License as

 * published by the Free Software Foundation; either version 2 of the

 * License, or (at your option) any later version.

 *

 * This program is distributed in the hope that it will be useful, but

 * WITHOUT ANY WARRANTY; without even the implied warranty of

 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU

 * General Public License for more details.

 *

 * You should have received a copy of the GNU General Public License

 * along with this program; if not, see <http://www.gnu.org/licenses/>.

 */



#include <linux/kernel.h>

#include <linux/module.h>

#include "meson_drv.h"

#include "meson_canvas.h"

#include "meson_registers.h"



/*

 * CANVAS is a memory zone where physical memory frames information

 * are stored for the VIU to scanout.

 */



/* DMC Registers */

#define DMC_CAV_LUT_DATAL	0x48 /* 0x12 offset in data sheet */

#define CANVAS_WIDTH_LBIT	29

#define CANVAS_WIDTH_LWID       3

#define DMC_CAV_LUT_DATAH	0x4c /* 0x13 offset in data sheet */

#define CANVAS_WIDTH_HBIT       0

#define CANVAS_HEIGHT_BIT       9

#define CANVAS_BLKMODE_BIT      24

#define DMC_CAV_LUT_ADDR	0x50 /* 0x14 offset in data sheet */

#define CANVAS_LUT_WR_EN        (0x2 << 8)

#define CANVAS_LUT_RD_EN        (0x1 << 8)



void meson_canvas_setup(struct meson_drm *priv,

			uint32_t canvas_index, uint32_t addr,

			uint32_t stride, uint32_t height,

			unsigned int wrap,

			unsigned int blkmode)

{

	unsigned int val;



	regmap_write(priv->dmc, DMC_CAV_LUT_DATAL,

		(((addr + 7) >> 3)) |

		(((stride + 7) >> 3) << CANVAS_WIDTH_LBIT));



	regmap_write(priv->dmc, DMC_CAV_LUT_DATAH,

		((((stride + 7) >> 3) >> CANVAS_WIDTH_LWID) <<

						CANVAS_WIDTH_HBIT) |

		(height << CANVAS_HEIGHT_BIT) |

		(wrap << 22) |

		(blkmode << CANVAS_BLKMODE_BIT));



	regmap_write(priv->dmc, DMC_CAV_LUT_ADDR,

			CANVAS_LUT_WR_EN | canvas_index);



	/* Force a read-back to make sure everything is flushed. */

	regmap_read(priv->dmc, DMC_CAV_LUT_DATAH, &val);

}