Commit a12c4967 authored Feb 04, 2014 by Ville Syrjälä Committed by Daniel Vetter Mar 04, 2014

drm/i915: Change HSW WIZ hashing mode to 16x4



BSpec recommends using 8x4 hashing mode when MSAA is used. But in
practice 16x4 seems to have a slight edge in performance (on IVB and
HSW at least). So just use 16x4.

Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Reviewed-by: Antti Koskipää <antti.koskipaa@linux.intel.com>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>

parent a607c1a4

drivers/gpu/drm/i915/intel_pm.c

+7 −0

Original line number	Diff line number	Diff line
		@@ -4873,6 +4873,13 @@ static void haswell_init_clock_gating(struct drm_device *dev)
		I915_WRITE(CACHE_MODE_1,
		_MASKED_BIT_ENABLE(PIXEL_SUBSPAN_COLLECT_OPT_DISABLE));

		/*
		* BSpec recommends 8x4 when MSAA is used,
		* however in practice 16x4 seems fastest.
		*/
		I915_WRITE(GEN7_GT_MODE,
		GEN6_WIZ_HASHING_MASK \| GEN6_WIZ_HASHING_16x4);

		/* WaSwitchSolVfFArbitrationPriority:hsw */
		I915_WRITE(GAM_ECOCHK, I915_READ(GAM_ECOCHK) \| HSW_ECOCHK_ARB_PRIO_SOL);