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Commit a607c1a4 authored by Ville Syrjälä's avatar Ville Syrjälä Committed by Daniel Vetter
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drm/i915: Change IVB WIZ hashing mode to 16x4 



BSpec recommends using 8x4 hashing mode when MSAA is used. But in
practice 16x4 seems to have a slight edge in performance (on IVB and
HSW at least). So just use 16x4.

Signed-off-by: default avatarVille Syrjälä <ville.syrjala@linux.intel.com>
Reviewed-by: default avatarAntti Koskipää <antti.koskipaa@linux.intel.com>
Signed-off-by: default avatarDaniel Vetter <daniel.vetter@ffwll.ch>
parent 743b57d8

drivers/gpu/drm/i915/i915_reg.h

+1 −0
Original line number Diff line number Diff line
@@ -798,6 +798,7 @@ 
# define ASYNC_FLIP_PERF_DISABLE			(1 << 14)



#define GEN6_GT_MODE	0x20d0

#define GEN7_GT_MODE	0x7008

#define   GEN6_WIZ_HASHING(hi, lo)			(((hi) << 9) | ((lo) << 7))

#define   GEN6_WIZ_HASHING_8x8				GEN6_WIZ_HASHING(0, 0)

#define   GEN6_WIZ_HASHING_8x4				GEN6_WIZ_HASHING(0, 1)

drivers/gpu/drm/i915/intel_pm.c

+7 −0
Original line number Diff line number Diff line
@@ -4954,6 +4954,13 @@ static void ivybridge_init_clock_gating(struct drm_device *dev) 
	I915_WRITE(CACHE_MODE_1,

		   _MASKED_BIT_ENABLE(PIXEL_SUBSPAN_COLLECT_OPT_DISABLE));



	/*

	 * BSpec recommends 8x4 when MSAA is used,

	 * however in practice 16x4 seems fastest.

	 */

	I915_WRITE(GEN7_GT_MODE,

		   GEN6_WIZ_HASHING_MASK | GEN6_WIZ_HASHING_16x4);



	snpcr = I915_READ(GEN6_MBCUNIT_SNPCR);

	snpcr &= ~GEN6_MBC_SNPCR_MASK;

	snpcr |= GEN6_MBC_SNPCR_MED;