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Commit a11fd208 authored by qctecmdr's avatar qctecmdr Committed by Gerrit - the friendly Code Review server
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Merge "ARM: dts: msm: Add DPC and dmips properties for Lito"

parents 7fd52331 7ab8bac5

qcom/lito.dtsi

+16 −0
Original line number Diff line number Diff line
@@ -43,6 +43,8 @@ 
			compatible = "arm,armv8";

			reg = <0x0 0x0>;

			enable-method = "psci";

			capacity-dmips-mhz = <1024>;

			dynamic-power-coefficient = <100>;

			cache-size = <0x8000>;

			qcom,freq-domain = <&cpufreq_hw 0 6>;

			next-level-cache = <&L2_0>;
@@ -79,6 +81,8 @@ 
			compatible = "arm,armv8";

			reg = <0x0 0x100>;

			enable-method = "psci";

			capacity-dmips-mhz = <1024>;

			dynamic-power-coefficient = <100>;

			cache-size = <0x8000>;

			qcom,freq-domain = <&cpufreq_hw 0 6>;

			next-level-cache = <&L2_100>;
@@ -109,6 +113,8 @@ 
			compatible = "arm,armv8";

			reg = <0x0 0x200>;

			enable-method = "psci";

			capacity-dmips-mhz = <1024>;

			dynamic-power-coefficient = <100>;

			cache-size = <0x8000>;

			qcom,freq-domain = <&cpufreq_hw 0 6>;

			next-level-cache = <&L2_200>;
@@ -139,6 +145,8 @@ 
			compatible = "arm,armv8";

			reg = <0x0 0x300>;

			enable-method = "psci";

			capacity-dmips-mhz = <1024>;

			dynamic-power-coefficient = <100>;

			cache-size = <0x8000>;

			qcom,freq-domain = <&cpufreq_hw 0 6>;

			next-level-cache = <&L2_300>;
@@ -170,6 +178,8 @@ 
			compatible = "arm,armv8";

			reg = <0x0 0x400>;

			enable-method = "psci";

			capacity-dmips-mhz = <1024>;

			dynamic-power-coefficient = <100>;

			cache-size = <0x8000>;

			qcom,freq-domain = <&cpufreq_hw 0 6>;

			next-level-cache = <&L2_400>;
@@ -200,6 +210,8 @@ 
			compatible = "arm,armv8";

			reg = <0x0 0x500>;

			enable-method = "psci";

			capacity-dmips-mhz = <1024>;

			dynamic-power-coefficient = <100>;

			cache-size = <0x8000>;

			qcom,freq-domain = <&cpufreq_hw 0 6>;

			next-level-cache = <&L2_500>;
@@ -230,6 +242,8 @@ 
			compatible = "arm,armv8";

			reg = <0x0 0x600>;

			enable-method = "psci";

			capacity-dmips-mhz = <1740>;

			dynamic-power-coefficient = <341>;

			cache-size = <0x10000>;

			qcom,freq-domain = <&cpufreq_hw 1 2>;

			next-level-cache = <&L2_600>;
@@ -269,6 +283,8 @@ 
			compatible = "arm,armv8";

			reg = <0x0 0x700>;

			enable-method = "psci";

			capacity-dmips-mhz = <1740>;

			dynamic-power-coefficient = <375>;

			cache-size = <0x10000>;

			qcom,freq-domain = <&cpufreq_hw 2 2>;

			next-level-cache = <&L2_700>;