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Commit 7ab8bac5 authored by Lingutla Chandrasekhar's avatar Lingutla Chandrasekhar
Browse files

ARM: dts: msm: Add DPC and dmips properties for Lito 

Add "dynamic-power-coefficient" and "capacity-dmips-mhz" for Lito,
these are used to build Energy Model, which in turn used by EAS to
take placement decisions.

Change-Id: I5d5c92b845bcc33a23a420b8198962d3b05b07bb
parent d2b4d028

qcom/lito.dtsi

+16 −0
Original line number Diff line number Diff line
@@ -40,6 +40,8 @@ 
			compatible = "arm,armv8";

			reg = <0x0 0x0>;

			enable-method = "psci";

			capacity-dmips-mhz = <1024>;

			dynamic-power-coefficient = <100>;

			cache-size = <0x8000>;

			next-level-cache = <&L2_0>;

			L2_0: l2-cache {
@@ -75,6 +77,8 @@ 
			compatible = "arm,armv8";

			reg = <0x0 0x100>;

			enable-method = "psci";

			capacity-dmips-mhz = <1024>;

			dynamic-power-coefficient = <100>;

			cache-size = <0x8000>;

			next-level-cache = <&L2_100>;

			L2_100: l2-cache {
@@ -104,6 +108,8 @@ 
			compatible = "arm,armv8";

			reg = <0x0 0x200>;

			enable-method = "psci";

			capacity-dmips-mhz = <1024>;

			dynamic-power-coefficient = <100>;

			cache-size = <0x8000>;

			next-level-cache = <&L2_200>;

			L2_200: l2-cache {
@@ -133,6 +139,8 @@ 
			compatible = "arm,armv8";

			reg = <0x0 0x300>;

			enable-method = "psci";

			capacity-dmips-mhz = <1024>;

			dynamic-power-coefficient = <100>;

			cache-size = <0x8000>;

			next-level-cache = <&L2_300>;

			L2_300: l2-cache {
@@ -163,6 +171,8 @@ 
			compatible = "arm,armv8";

			reg = <0x0 0x400>;

			enable-method = "psci";

			capacity-dmips-mhz = <1024>;

			dynamic-power-coefficient = <100>;

			cache-size = <0x8000>;

			next-level-cache = <&L2_400>;

			L2_400: l2-cache {
@@ -192,6 +202,8 @@ 
			compatible = "arm,armv8";

			reg = <0x0 0x500>;

			enable-method = "psci";

			capacity-dmips-mhz = <1024>;

			dynamic-power-coefficient = <100>;

			cache-size = <0x8000>;

			next-level-cache = <&L2_500>;

			L2_500: l2-cache {
@@ -221,6 +233,8 @@ 
			compatible = "arm,armv8";

			reg = <0x0 0x600>;

			enable-method = "psci";

			capacity-dmips-mhz = <1740>;

			dynamic-power-coefficient = <341>;

			cache-size = <0x10000>;

			next-level-cache = <&L2_600>;

			L2_600: l2-cache {
@@ -259,6 +273,8 @@ 
			compatible = "arm,armv8";

			reg = <0x0 0x700>;

			enable-method = "psci";

			capacity-dmips-mhz = <1740>;

			dynamic-power-coefficient = <375>;

			cache-size = <0x10000>;

			next-level-cache = <&L2_700>;

			L2_700: l2-cache {