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Commit a0307d18 authored by Chris Zhong's avatar Chris Zhong Committed by Heiko Stuebner
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ARM: rockchip: disable watchdog during suspend 



The watchdog clock should be disable in dw_wdt_suspend, but we set a
dummy clock to watchdog for rk3288. So the watchdog will continue to
work during suspend. And we switch the system clock to 32khz from 24Mhz,
during suspend, so the watchdog timer over count will increase to
755 times, about 12.5 hours, the original value is 60 seconds. So
watchdog will reset the system over a night,  but voltage are all
incorrect, then it hang on reset.

Signed-off-by: default avatarChris Zhong <zyw@rock-chips.com>
Signed-off-by: default avatarDaniel Kurtz <djkurtz@google.com>
Reviewed-by: default avatarDoug Anderson <dianders@chromium.org>
Tested-by: default avatarDoug Anderson <dianders@chromium.org>
Signed-off-by: default avatarHeiko Stuebner <heiko@sntech.de>
parent aefc7c75

arch/arm/mach-rockchip/pm.c

+8 −3
Original line number Diff line number Diff line
@@ -75,9 +75,13 @@ static void rk3288_slp_mode_set(int level) 
	regmap_read(pmu_regmap, RK3288_PMU_PWRMODE_CON,

		    &rk3288_pmu_pwr_mode_con);



	/* set bit 8 so that system will resume to FAST_BOOT_ADDR */

	/*

	 * SGRF_FAST_BOOT_EN - system to boot from FAST_BOOT_ADDR

	 * PCLK_WDT_GATE - disable WDT during suspend.

	 */

	regmap_write(sgrf_regmap, RK3288_SGRF_SOC_CON0,

		     SGRF_FAST_BOOT_EN | SGRF_FAST_BOOT_EN_WRITE);

		     SGRF_PCLK_WDT_GATE | SGRF_FAST_BOOT_EN

		     | SGRF_PCLK_WDT_GATE_WRITE | SGRF_FAST_BOOT_EN_WRITE);



	/* booting address of resuming system is from this register value */

	regmap_write(sgrf_regmap, RK3288_SGRF_FAST_BOOT_ADDR,
@@ -122,7 +126,8 @@ static void rk3288_slp_mode_set_resume(void) 
		     rk3288_pmu_pwr_mode_con);



	regmap_write(sgrf_regmap, RK3288_SGRF_SOC_CON0,

		     rk3288_sgrf_soc_con0 | SGRF_FAST_BOOT_EN_WRITE);

		     rk3288_sgrf_soc_con0 | SGRF_PCLK_WDT_GATE_WRITE

		     | SGRF_FAST_BOOT_EN_WRITE);

}



static int rockchip_lpmode_enter(unsigned long arg)

arch/arm/mach-rockchip/pm.h

+2 −0
Original line number Diff line number Diff line
@@ -50,6 +50,8 @@ static inline void rockchip_suspend_init(void) 


#define RK3288_SGRF_SOC_CON0		(0x0000)

#define RK3288_SGRF_FAST_BOOT_ADDR	(0x0120)

#define SGRF_PCLK_WDT_GATE		BIT(6)

#define SGRF_PCLK_WDT_GATE_WRITE	BIT(22)

#define SGRF_FAST_BOOT_EN		BIT(8)

#define SGRF_FAST_BOOT_EN_WRITE		BIT(24)