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Commit aefc7c75 authored by Chris Zhong's avatar Chris Zhong Committed by Heiko Stuebner
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ARM: rockchip: decrease the wait time for resume 



The register-default delay time for wait the 24MHz OSC stabilization as well
as PMU stabilization is 750ms, let's decrease them to a still safe 30ms.

Signed-off-by: default avatarChris Zhong <zyw@rock-chips.com>
Reviewed-by: default avatarDoug Anderson <dianders@chromium.org>
Tested-by: default avatarDoug Anderson <dianders@chromium.org>
Signed-off-by: default avatarHeiko Stuebner <heiko@sntech.de>
parent bd76d738

arch/arm/mach-rockchip/pm.c

+3 −0
Original line number Diff line number Diff line
@@ -209,6 +209,9 @@ static int rk3288_suspend_init(struct device_node *np) 
	memcpy(rk3288_bootram_base, rockchip_slp_cpu_resume,

	       rk3288_bootram_sz);



	regmap_write(pmu_regmap, RK3288_PMU_OSC_CNT, OSC_STABL_CNT_THRESH);

	regmap_write(pmu_regmap, RK3288_PMU_STABL_CNT, PMU_STABL_CNT_THRESH);



	return 0;

}

arch/arm/mach-rockchip/pm.h

+4 −0
Original line number Diff line number Diff line
@@ -63,6 +63,10 @@ static inline void rockchip_suspend_init(void) 
/* PMU_WAKEUP_CFG1 bits */

#define PMU_ARMINT_WAKEUP_EN		BIT(0)



/* wait 30ms for OSC stable and 30ms for pmic stable */

#define OSC_STABL_CNT_THRESH	(32 * 30)

#define PMU_STABL_CNT_THRESH	(32 * 30)



enum rk3288_pwr_mode_con {

	PMU_PWR_MODE_EN = 0,

	PMU_CLK_CORE_SRC_GATE_EN,