Loading drivers/gpu/drm/vc4/vc4_crtc.c +22 −10 Original line number Original line Diff line number Diff line Loading @@ -456,14 +456,6 @@ static void vc4_crtc_atomic_flush(struct drm_crtc *crtc, WARN_ON_ONCE(dlist_next - dlist_start != vc4_state->mm.size); WARN_ON_ONCE(dlist_next - dlist_start != vc4_state->mm.size); HVS_WRITE(SCALER_DISPLISTX(vc4_crtc->channel), vc4_state->mm.start); if (debug_dump_regs) { DRM_INFO("CRTC %d HVS after:\n", drm_crtc_index(crtc)); vc4_hvs_dump_state(dev); } if (crtc->state->event) { if (crtc->state->event) { unsigned long flags; unsigned long flags; Loading @@ -473,8 +465,20 @@ static void vc4_crtc_atomic_flush(struct drm_crtc *crtc, spin_lock_irqsave(&dev->event_lock, flags); spin_lock_irqsave(&dev->event_lock, flags); vc4_crtc->event = crtc->state->event; vc4_crtc->event = crtc->state->event; spin_unlock_irqrestore(&dev->event_lock, flags); crtc->state->event = NULL; crtc->state->event = NULL; HVS_WRITE(SCALER_DISPLISTX(vc4_crtc->channel), vc4_state->mm.start); spin_unlock_irqrestore(&dev->event_lock, flags); } else { HVS_WRITE(SCALER_DISPLISTX(vc4_crtc->channel), vc4_state->mm.start); } if (debug_dump_regs) { DRM_INFO("CRTC %d HVS after:\n", drm_crtc_index(crtc)); vc4_hvs_dump_state(dev); } } } } Loading @@ -500,12 +504,17 @@ static void vc4_crtc_handle_page_flip(struct vc4_crtc *vc4_crtc) { { struct drm_crtc *crtc = &vc4_crtc->base; struct drm_crtc *crtc = &vc4_crtc->base; struct drm_device *dev = crtc->dev; struct drm_device *dev = crtc->dev; struct vc4_dev *vc4 = to_vc4_dev(dev); struct vc4_crtc_state *vc4_state = to_vc4_crtc_state(crtc->state); u32 chan = vc4_crtc->channel; unsigned long flags; unsigned long flags; spin_lock_irqsave(&dev->event_lock, flags); spin_lock_irqsave(&dev->event_lock, flags); if (vc4_crtc->event) { if (vc4_crtc->event && (vc4_state->mm.start == HVS_READ(SCALER_DISPLACTX(chan)))) { drm_crtc_send_vblank_event(crtc, vc4_crtc->event); drm_crtc_send_vblank_event(crtc, vc4_crtc->event); vc4_crtc->event = NULL; vc4_crtc->event = NULL; drm_crtc_vblank_put(crtc); } } spin_unlock_irqrestore(&dev->event_lock, flags); spin_unlock_irqrestore(&dev->event_lock, flags); } } Loading Loading @@ -556,6 +565,7 @@ vc4_async_page_flip_complete(struct vc4_seqno_cb *cb) spin_unlock_irqrestore(&dev->event_lock, flags); spin_unlock_irqrestore(&dev->event_lock, flags); } } drm_crtc_vblank_put(crtc); drm_framebuffer_unreference(flip_state->fb); drm_framebuffer_unreference(flip_state->fb); kfree(flip_state); kfree(flip_state); Loading Loading @@ -598,6 +608,8 @@ static int vc4_async_page_flip(struct drm_crtc *crtc, return ret; return ret; } } WARN_ON(drm_crtc_vblank_get(crtc) != 0); /* Immediately update the plane's legacy fb pointer, so that later /* Immediately update the plane's legacy fb pointer, so that later * modeset prep sees the state that will be present when the semaphore * modeset prep sees the state that will be present when the semaphore * is released. * is released. Loading drivers/gpu/drm/vc4/vc4_drv.c +7 −7 Original line number Original line Diff line number Diff line Loading @@ -66,12 +66,12 @@ static const struct file_operations vc4_drm_fops = { }; }; static const struct drm_ioctl_desc vc4_drm_ioctls[] = { static const struct drm_ioctl_desc vc4_drm_ioctls[] = { DRM_IOCTL_DEF_DRV(VC4_SUBMIT_CL, vc4_submit_cl_ioctl, 0), DRM_IOCTL_DEF_DRV(VC4_SUBMIT_CL, vc4_submit_cl_ioctl, DRM_RENDER_ALLOW), DRM_IOCTL_DEF_DRV(VC4_WAIT_SEQNO, vc4_wait_seqno_ioctl, 0), DRM_IOCTL_DEF_DRV(VC4_WAIT_SEQNO, vc4_wait_seqno_ioctl, DRM_RENDER_ALLOW), DRM_IOCTL_DEF_DRV(VC4_WAIT_BO, vc4_wait_bo_ioctl, 0), DRM_IOCTL_DEF_DRV(VC4_WAIT_BO, vc4_wait_bo_ioctl, DRM_RENDER_ALLOW), DRM_IOCTL_DEF_DRV(VC4_CREATE_BO, vc4_create_bo_ioctl, 0), DRM_IOCTL_DEF_DRV(VC4_CREATE_BO, vc4_create_bo_ioctl, DRM_RENDER_ALLOW), DRM_IOCTL_DEF_DRV(VC4_MMAP_BO, vc4_mmap_bo_ioctl, 0), DRM_IOCTL_DEF_DRV(VC4_MMAP_BO, vc4_mmap_bo_ioctl, DRM_RENDER_ALLOW), DRM_IOCTL_DEF_DRV(VC4_CREATE_SHADER_BO, vc4_create_shader_bo_ioctl, 0), DRM_IOCTL_DEF_DRV(VC4_CREATE_SHADER_BO, vc4_create_shader_bo_ioctl, DRM_RENDER_ALLOW), DRM_IOCTL_DEF_DRV(VC4_GET_HANG_STATE, vc4_get_hang_state_ioctl, DRM_IOCTL_DEF_DRV(VC4_GET_HANG_STATE, vc4_get_hang_state_ioctl, DRM_ROOT_ONLY), DRM_ROOT_ONLY), }; }; Loading @@ -91,7 +91,7 @@ static struct drm_driver vc4_drm_driver = { .enable_vblank = vc4_enable_vblank, .enable_vblank = vc4_enable_vblank, .disable_vblank = vc4_disable_vblank, .disable_vblank = vc4_disable_vblank, .get_vblank_counter = drm_vblank_count, .get_vblank_counter = drm_vblank_no_hw_counter, #if defined(CONFIG_DEBUG_FS) #if defined(CONFIG_DEBUG_FS) .debugfs_init = vc4_debugfs_init, .debugfs_init = vc4_debugfs_init, Loading drivers/gpu/drm/vc4/vc4_kms.c +12 −4 Original line number Original line Diff line number Diff line Loading @@ -117,11 +117,19 @@ static int vc4_atomic_commit(struct drm_device *dev, return -ENOMEM; return -ENOMEM; /* Make sure that any outstanding modesets have finished. */ /* Make sure that any outstanding modesets have finished. */ if (nonblock) { ret = down_trylock(&vc4->async_modeset); if (ret) { kfree(c); return -EBUSY; } } else { ret = down_interruptible(&vc4->async_modeset); ret = down_interruptible(&vc4->async_modeset); if (ret) { if (ret) { kfree(c); kfree(c); return ret; return ret; } } } ret = drm_atomic_helper_prepare_planes(dev, state); ret = drm_atomic_helper_prepare_planes(dev, state); if (ret) { if (ret) { Loading drivers/gpu/drm/vc4/vc4_regs.h +4 −0 Original line number Original line Diff line number Diff line Loading @@ -341,6 +341,10 @@ #define SCALER_DISPLACT0 0x00000030 #define SCALER_DISPLACT0 0x00000030 #define SCALER_DISPLACT1 0x00000034 #define SCALER_DISPLACT1 0x00000034 #define SCALER_DISPLACT2 0x00000038 #define SCALER_DISPLACT2 0x00000038 #define SCALER_DISPLACTX(x) (SCALER_DISPLACT0 + \ (x) * (SCALER_DISPLACT1 - \ SCALER_DISPLACT0)) #define SCALER_DISPCTRL0 0x00000040 #define SCALER_DISPCTRL0 0x00000040 # define SCALER_DISPCTRLX_ENABLE BIT(31) # define SCALER_DISPCTRLX_ENABLE BIT(31) # define SCALER_DISPCTRLX_RESET BIT(30) # define SCALER_DISPCTRLX_RESET BIT(30) Loading Loading
drivers/gpu/drm/vc4/vc4_crtc.c +22 −10 Original line number Original line Diff line number Diff line Loading @@ -456,14 +456,6 @@ static void vc4_crtc_atomic_flush(struct drm_crtc *crtc, WARN_ON_ONCE(dlist_next - dlist_start != vc4_state->mm.size); WARN_ON_ONCE(dlist_next - dlist_start != vc4_state->mm.size); HVS_WRITE(SCALER_DISPLISTX(vc4_crtc->channel), vc4_state->mm.start); if (debug_dump_regs) { DRM_INFO("CRTC %d HVS after:\n", drm_crtc_index(crtc)); vc4_hvs_dump_state(dev); } if (crtc->state->event) { if (crtc->state->event) { unsigned long flags; unsigned long flags; Loading @@ -473,8 +465,20 @@ static void vc4_crtc_atomic_flush(struct drm_crtc *crtc, spin_lock_irqsave(&dev->event_lock, flags); spin_lock_irqsave(&dev->event_lock, flags); vc4_crtc->event = crtc->state->event; vc4_crtc->event = crtc->state->event; spin_unlock_irqrestore(&dev->event_lock, flags); crtc->state->event = NULL; crtc->state->event = NULL; HVS_WRITE(SCALER_DISPLISTX(vc4_crtc->channel), vc4_state->mm.start); spin_unlock_irqrestore(&dev->event_lock, flags); } else { HVS_WRITE(SCALER_DISPLISTX(vc4_crtc->channel), vc4_state->mm.start); } if (debug_dump_regs) { DRM_INFO("CRTC %d HVS after:\n", drm_crtc_index(crtc)); vc4_hvs_dump_state(dev); } } } } Loading @@ -500,12 +504,17 @@ static void vc4_crtc_handle_page_flip(struct vc4_crtc *vc4_crtc) { { struct drm_crtc *crtc = &vc4_crtc->base; struct drm_crtc *crtc = &vc4_crtc->base; struct drm_device *dev = crtc->dev; struct drm_device *dev = crtc->dev; struct vc4_dev *vc4 = to_vc4_dev(dev); struct vc4_crtc_state *vc4_state = to_vc4_crtc_state(crtc->state); u32 chan = vc4_crtc->channel; unsigned long flags; unsigned long flags; spin_lock_irqsave(&dev->event_lock, flags); spin_lock_irqsave(&dev->event_lock, flags); if (vc4_crtc->event) { if (vc4_crtc->event && (vc4_state->mm.start == HVS_READ(SCALER_DISPLACTX(chan)))) { drm_crtc_send_vblank_event(crtc, vc4_crtc->event); drm_crtc_send_vblank_event(crtc, vc4_crtc->event); vc4_crtc->event = NULL; vc4_crtc->event = NULL; drm_crtc_vblank_put(crtc); } } spin_unlock_irqrestore(&dev->event_lock, flags); spin_unlock_irqrestore(&dev->event_lock, flags); } } Loading Loading @@ -556,6 +565,7 @@ vc4_async_page_flip_complete(struct vc4_seqno_cb *cb) spin_unlock_irqrestore(&dev->event_lock, flags); spin_unlock_irqrestore(&dev->event_lock, flags); } } drm_crtc_vblank_put(crtc); drm_framebuffer_unreference(flip_state->fb); drm_framebuffer_unreference(flip_state->fb); kfree(flip_state); kfree(flip_state); Loading Loading @@ -598,6 +608,8 @@ static int vc4_async_page_flip(struct drm_crtc *crtc, return ret; return ret; } } WARN_ON(drm_crtc_vblank_get(crtc) != 0); /* Immediately update the plane's legacy fb pointer, so that later /* Immediately update the plane's legacy fb pointer, so that later * modeset prep sees the state that will be present when the semaphore * modeset prep sees the state that will be present when the semaphore * is released. * is released. Loading
drivers/gpu/drm/vc4/vc4_drv.c +7 −7 Original line number Original line Diff line number Diff line Loading @@ -66,12 +66,12 @@ static const struct file_operations vc4_drm_fops = { }; }; static const struct drm_ioctl_desc vc4_drm_ioctls[] = { static const struct drm_ioctl_desc vc4_drm_ioctls[] = { DRM_IOCTL_DEF_DRV(VC4_SUBMIT_CL, vc4_submit_cl_ioctl, 0), DRM_IOCTL_DEF_DRV(VC4_SUBMIT_CL, vc4_submit_cl_ioctl, DRM_RENDER_ALLOW), DRM_IOCTL_DEF_DRV(VC4_WAIT_SEQNO, vc4_wait_seqno_ioctl, 0), DRM_IOCTL_DEF_DRV(VC4_WAIT_SEQNO, vc4_wait_seqno_ioctl, DRM_RENDER_ALLOW), DRM_IOCTL_DEF_DRV(VC4_WAIT_BO, vc4_wait_bo_ioctl, 0), DRM_IOCTL_DEF_DRV(VC4_WAIT_BO, vc4_wait_bo_ioctl, DRM_RENDER_ALLOW), DRM_IOCTL_DEF_DRV(VC4_CREATE_BO, vc4_create_bo_ioctl, 0), DRM_IOCTL_DEF_DRV(VC4_CREATE_BO, vc4_create_bo_ioctl, DRM_RENDER_ALLOW), DRM_IOCTL_DEF_DRV(VC4_MMAP_BO, vc4_mmap_bo_ioctl, 0), DRM_IOCTL_DEF_DRV(VC4_MMAP_BO, vc4_mmap_bo_ioctl, DRM_RENDER_ALLOW), DRM_IOCTL_DEF_DRV(VC4_CREATE_SHADER_BO, vc4_create_shader_bo_ioctl, 0), DRM_IOCTL_DEF_DRV(VC4_CREATE_SHADER_BO, vc4_create_shader_bo_ioctl, DRM_RENDER_ALLOW), DRM_IOCTL_DEF_DRV(VC4_GET_HANG_STATE, vc4_get_hang_state_ioctl, DRM_IOCTL_DEF_DRV(VC4_GET_HANG_STATE, vc4_get_hang_state_ioctl, DRM_ROOT_ONLY), DRM_ROOT_ONLY), }; }; Loading @@ -91,7 +91,7 @@ static struct drm_driver vc4_drm_driver = { .enable_vblank = vc4_enable_vblank, .enable_vblank = vc4_enable_vblank, .disable_vblank = vc4_disable_vblank, .disable_vblank = vc4_disable_vblank, .get_vblank_counter = drm_vblank_count, .get_vblank_counter = drm_vblank_no_hw_counter, #if defined(CONFIG_DEBUG_FS) #if defined(CONFIG_DEBUG_FS) .debugfs_init = vc4_debugfs_init, .debugfs_init = vc4_debugfs_init, Loading
drivers/gpu/drm/vc4/vc4_kms.c +12 −4 Original line number Original line Diff line number Diff line Loading @@ -117,11 +117,19 @@ static int vc4_atomic_commit(struct drm_device *dev, return -ENOMEM; return -ENOMEM; /* Make sure that any outstanding modesets have finished. */ /* Make sure that any outstanding modesets have finished. */ if (nonblock) { ret = down_trylock(&vc4->async_modeset); if (ret) { kfree(c); return -EBUSY; } } else { ret = down_interruptible(&vc4->async_modeset); ret = down_interruptible(&vc4->async_modeset); if (ret) { if (ret) { kfree(c); kfree(c); return ret; return ret; } } } ret = drm_atomic_helper_prepare_planes(dev, state); ret = drm_atomic_helper_prepare_planes(dev, state); if (ret) { if (ret) { Loading
drivers/gpu/drm/vc4/vc4_regs.h +4 −0 Original line number Original line Diff line number Diff line Loading @@ -341,6 +341,10 @@ #define SCALER_DISPLACT0 0x00000030 #define SCALER_DISPLACT0 0x00000030 #define SCALER_DISPLACT1 0x00000034 #define SCALER_DISPLACT1 0x00000034 #define SCALER_DISPLACT2 0x00000038 #define SCALER_DISPLACT2 0x00000038 #define SCALER_DISPLACTX(x) (SCALER_DISPLACT0 + \ (x) * (SCALER_DISPLACT1 - \ SCALER_DISPLACT0)) #define SCALER_DISPCTRL0 0x00000040 #define SCALER_DISPCTRL0 0x00000040 # define SCALER_DISPCTRLX_ENABLE BIT(31) # define SCALER_DISPCTRLX_ENABLE BIT(31) # define SCALER_DISPCTRLX_RESET BIT(30) # define SCALER_DISPCTRLX_RESET BIT(30) Loading