Loading drivers/clk/qcom/npucc-kona.c +7 −0 Original line number Diff line number Diff line Loading @@ -298,6 +298,7 @@ static struct clk_rcg2 npu_cc_cal_hm1_clk_src = { .parent_map = npu_cc_parent_map_0_crc, .freq_tbl = ftbl_npu_cc_cal_hm0_clk_src, .enable_safe_config = true, .flags = HW_CLK_CTRL_MODE, .clkr.hw.init = &(struct clk_init_data){ .name = "npu_cc_cal_hm1_clk_src", .parent_names = npu_cc_parent_names_0_crc, Loading @@ -323,6 +324,7 @@ static struct clk_rcg2 npu_cc_cal_hm0_clk_src = { .parent_map = npu_cc_parent_map_0_crc, .freq_tbl = ftbl_npu_cc_cal_hm0_clk_src, .enable_safe_config = true, .flags = HW_CLK_CTRL_MODE, .clkr = { .hw.init = &(struct clk_init_data){ .name = "npu_cc_cal_hm0_clk_src", Loading Loading @@ -366,6 +368,7 @@ static struct clk_rcg2 npu_cc_core_clk_src = { .parent_map = npu_cc_parent_map_0, .freq_tbl = ftbl_npu_cc_core_clk_src, .enable_safe_config = true, .flags = HW_CLK_CTRL_MODE, .clkr.hw.init = &(struct clk_init_data){ .name = "npu_cc_core_clk_src", .parent_names = npu_cc_parent_names_0, Loading Loading @@ -399,6 +402,8 @@ static struct clk_rcg2 npu_cc_lmh_clk_src = { .hid_width = 5, .parent_map = npu_cc_parent_map_0, .freq_tbl = ftbl_npu_cc_lmh_clk_src, .enable_safe_config = true, .flags = HW_CLK_CTRL_MODE, .clkr.hw.init = &(struct clk_init_data){ .name = "npu_cc_lmh_clk_src", .parent_names = npu_cc_parent_names_0, Loading Loading @@ -451,6 +456,8 @@ static struct clk_rcg2 npu_dsp_core_clk_src = { .hid_width = 5, .parent_map = npu_cc_parent_map_2, .freq_tbl = ftbl_npu_dsp_core_clk_src, .enable_safe_config = true, .flags = HW_CLK_CTRL_MODE, .clkr.hw.init = &(struct clk_init_data){ .name = "npu_dsp_core_clk_src", .parent_names = npu_cc_parent_names_2, Loading Loading
drivers/clk/qcom/npucc-kona.c +7 −0 Original line number Diff line number Diff line Loading @@ -298,6 +298,7 @@ static struct clk_rcg2 npu_cc_cal_hm1_clk_src = { .parent_map = npu_cc_parent_map_0_crc, .freq_tbl = ftbl_npu_cc_cal_hm0_clk_src, .enable_safe_config = true, .flags = HW_CLK_CTRL_MODE, .clkr.hw.init = &(struct clk_init_data){ .name = "npu_cc_cal_hm1_clk_src", .parent_names = npu_cc_parent_names_0_crc, Loading @@ -323,6 +324,7 @@ static struct clk_rcg2 npu_cc_cal_hm0_clk_src = { .parent_map = npu_cc_parent_map_0_crc, .freq_tbl = ftbl_npu_cc_cal_hm0_clk_src, .enable_safe_config = true, .flags = HW_CLK_CTRL_MODE, .clkr = { .hw.init = &(struct clk_init_data){ .name = "npu_cc_cal_hm0_clk_src", Loading Loading @@ -366,6 +368,7 @@ static struct clk_rcg2 npu_cc_core_clk_src = { .parent_map = npu_cc_parent_map_0, .freq_tbl = ftbl_npu_cc_core_clk_src, .enable_safe_config = true, .flags = HW_CLK_CTRL_MODE, .clkr.hw.init = &(struct clk_init_data){ .name = "npu_cc_core_clk_src", .parent_names = npu_cc_parent_names_0, Loading Loading @@ -399,6 +402,8 @@ static struct clk_rcg2 npu_cc_lmh_clk_src = { .hid_width = 5, .parent_map = npu_cc_parent_map_0, .freq_tbl = ftbl_npu_cc_lmh_clk_src, .enable_safe_config = true, .flags = HW_CLK_CTRL_MODE, .clkr.hw.init = &(struct clk_init_data){ .name = "npu_cc_lmh_clk_src", .parent_names = npu_cc_parent_names_0, Loading Loading @@ -451,6 +456,8 @@ static struct clk_rcg2 npu_dsp_core_clk_src = { .hid_width = 5, .parent_map = npu_cc_parent_map_2, .freq_tbl = ftbl_npu_dsp_core_clk_src, .enable_safe_config = true, .flags = HW_CLK_CTRL_MODE, .clkr.hw.init = &(struct clk_init_data){ .name = "npu_dsp_core_clk_src", .parent_names = npu_cc_parent_names_2, Loading