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Commit 9d33e0c2 authored by Raviteja Tamatam's avatar Raviteja Tamatam
Browse files

disp: msm: sde: update BW_INDICATION programing sequence 



BW_INDICATION indication must be programed before BWI_THRESHOLD.
Otherwise, it will revert to legacy behaviour and rsc wakeup is
delayed by one vsync causing janks. In current code BW_INDICATION
is done after LM/SSPP programming and plane fence wait. Moved the
perf_crtc_update before this and just after ctl prepare configuration
to avoid chances of BW_INDICATION crossing BWI_THRESHOLD time.

Change-Id: Ie976720910c34aaf140f1ce7daef38ba20bc10f5
Signed-off-by: default avatarRaviteja Tamatam <travitej@codeaurora.org>
parent e2be37e0

msm/sde/sde_crtc.c

+3 −3
Original line number Diff line number Diff line
@@ -3126,6 +3126,9 @@ static void sde_crtc_atomic_begin(struct drm_crtc *crtc, 
		sde_encoder_trigger_kickoff_pending(encoder);

	}



	/* update performance setting */

	sde_core_perf_crtc_update(crtc, 1, false);



	/*

	 * If no mixers have been allocated in sde_crtc_atomic_check(),

	 * it means we are trying to flush a CRTC whose state is disabled:
@@ -3273,9 +3276,6 @@ static void sde_crtc_atomic_flush(struct drm_crtc *crtc, 
		cstate->rsc_update = true;

	}



	/* update performance setting before crtc kickoff */

	sde_core_perf_crtc_update(crtc, 1, false);



	/*

	 * Final plane updates: Give each plane a chance to complete all

	 *                      required writes/flushing before crtc's "flush