Donate to e Foundation | Murena handsets with /e/OS | Own a part of Murena! Learn more

Commit 9bd9ddb7 authored by Jisheng Zhang's avatar Jisheng Zhang Committed by David S. Miller
Browse files

net: mvneta: replace MVNETA_CPU_D_CACHE_LINE_SIZE with L1_CACHE_BYTES 



The mvneta is also used in some Marvell berlin family SoCs which may
have 64bytes cacheline size. Replace the MVNETA_CPU_D_CACHE_LINE_SIZE
usage with L1_CACHE_BYTES.

And since dma_alloc_coherent() is always cacheline size aligned, so
remove the align checks.

Signed-off-by: default avatarJisheng Zhang <jszhang@marvell.com>
Signed-off-by: default avatarDavid S. Miller <davem@davemloft.net>
parent b7854efc

drivers/net/ethernet/marvell/mvneta.c

+1 −9
Original line number Diff line number Diff line
@@ -260,7 +260,6 @@ 


#define MVNETA_VLAN_TAG_LEN             4



#define MVNETA_CPU_D_CACHE_LINE_SIZE    32

#define MVNETA_TX_CSUM_DEF_SIZE		1600

#define MVNETA_TX_CSUM_MAX_SIZE		9800

#define MVNETA_ACC_MODE_EXT1		1
@@ -300,7 +299,7 @@ 
#define MVNETA_RX_PKT_SIZE(mtu) \

	ALIGN((mtu) + MVNETA_MH_SIZE + MVNETA_VLAN_TAG_LEN + \

	      ETH_HLEN + ETH_FCS_LEN,			     \

	      MVNETA_CPU_D_CACHE_LINE_SIZE)

	      L1_CACHE_BYTES)



#define IS_TSO_HEADER(txq, addr) \

	((addr >= txq->tso_hdrs_phys) && \
@@ -2764,9 +2763,6 @@ static int mvneta_rxq_init(struct mvneta_port *pp, 
	if (rxq->descs == NULL)

		return -ENOMEM;



	BUG_ON(rxq->descs !=

	       PTR_ALIGN(rxq->descs, MVNETA_CPU_D_CACHE_LINE_SIZE));



	rxq->last_desc = rxq->size - 1;



	/* Set Rx descriptors queue starting address */
@@ -2837,10 +2833,6 @@ static int mvneta_txq_init(struct mvneta_port *pp, 
	if (txq->descs == NULL)

		return -ENOMEM;



	/* Make sure descriptor address is cache line size aligned  */

	BUG_ON(txq->descs !=

	       PTR_ALIGN(txq->descs, MVNETA_CPU_D_CACHE_LINE_SIZE));



	txq->last_desc = txq->size - 1;



	/* Set maximum bandwidth for enabled TXQs */