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Commit b7854efc authored by Jisheng Zhang's avatar Jisheng Zhang Committed by David S. Miller
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net: mvpp2: replace MVPP2_CPU_D_CACHE_LINE_SIZE with L1_CACHE_BYTES 



The mvpp2 ip maybe used in SoCs which may have have 64bytes cacheline
size. Replace the MVPP2_CPU_D_CACHE_LINE_SIZE with L1_CACHE_BYTES.

And since dma_alloc_coherent() is always cacheline size aligned, so
remove the align checks.

Signed-off-by: default avatarJisheng Zhang <jszhang@marvell.com>
Signed-off-by: default avatarDavid S. Miller <davem@davemloft.net>
parent 13a7ebb3

drivers/net/ethernet/marvell/mvpp2.c

+1 −13
Original line number Diff line number Diff line
@@ -321,7 +321,6 @@ 
/* Lbtd 802.3 type */

#define MVPP2_IP_LBDT_TYPE		0xfffa



#define MVPP2_CPU_D_CACHE_LINE_SIZE	32

#define MVPP2_TX_CSUM_MAX_SIZE		9800



/* Timeout constants */
@@ -377,7 +376,7 @@ 


#define MVPP2_RX_PKT_SIZE(mtu) \

	ALIGN((mtu) + MVPP2_MH_SIZE + MVPP2_VLAN_TAG_LEN + \

	      ETH_HLEN + ETH_FCS_LEN, MVPP2_CPU_D_CACHE_LINE_SIZE)

	      ETH_HLEN + ETH_FCS_LEN, L1_CACHE_BYTES)



#define MVPP2_RX_BUF_SIZE(pkt_size)	((pkt_size) + NET_SKB_PAD)

#define MVPP2_RX_TOTAL_SIZE(buf_size)	((buf_size) + MVPP2_SKB_SHINFO_SIZE)
@@ -4493,10 +4492,6 @@ static int mvpp2_aggr_txq_init(struct platform_device *pdev, 
	if (!aggr_txq->descs)

		return -ENOMEM;



	/* Make sure descriptor address is cache line size aligned  */

	BUG_ON(aggr_txq->descs !=

	       PTR_ALIGN(aggr_txq->descs, MVPP2_CPU_D_CACHE_LINE_SIZE));



	aggr_txq->last_desc = aggr_txq->size - 1;



	/* Aggr TXQ no reset WA */
@@ -4526,9 +4521,6 @@ static int mvpp2_rxq_init(struct mvpp2_port *port, 
	if (!rxq->descs)

		return -ENOMEM;



	BUG_ON(rxq->descs !=

	       PTR_ALIGN(rxq->descs, MVPP2_CPU_D_CACHE_LINE_SIZE));



	rxq->last_desc = rxq->size - 1;



	/* Zero occupied and non-occupied counters - direct access */
@@ -4616,10 +4608,6 @@ static int mvpp2_txq_init(struct mvpp2_port *port, 
	if (!txq->descs)

		return -ENOMEM;



	/* Make sure descriptor address is cache line size aligned  */

	BUG_ON(txq->descs !=

	       PTR_ALIGN(txq->descs, MVPP2_CPU_D_CACHE_LINE_SIZE));



	txq->last_desc = txq->size - 1;



	/* Set Tx descriptors queue starting address - indirect access */