Commit 9a20b092 authored May 27, 2015 by Maciej W. Rozycki Committed by Ralf Baechle Jun 21, 2015

MIPS: tlb-r3k: Optimise a TLBWI barrier in TLB invalidation

Replace an explicit barrier with a useful processor instruction in TLB
invalidation, following several other such cases elsewhere in
`tlb-r3k.c'.

Signed-off-by: Maciej W. Rozycki <macro@linux-mips.org>
Cc: James Hogan <james.hogan@imgtec.com>
Cc: linux-mips@linux-mips.org
Patchwork: https://patchwork.linux-mips.org/patch/10196/

Signed-off-by: Ralf Baechle <ralf@linux-mips.org>

parent 3bcb03f3

arch/mips/mm/tlb-r3k.c

+2 −2

Original line number	Diff line number	Diff line
		@@ -45,10 +45,10 @@ static void local_flush_tlb_from(int entry)

		old_ctx = read_c0_entryhi() & ASID_MASK;
		write_c0_entrylo0(0);
		for (; entry < current_cpu_data.tlbsize; entry++) {
		while (entry < current_cpu_data.tlbsize) {
		write_c0_index(entry << 8);
		write_c0_entryhi((entry \| 0x80000) << 12);
		BARRIER;
		entry++; /* BARRIER */
		tlb_write_indexed();
		}
		write_c0_entryhi(old_ctx);