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Commit 3bcb03f3 authored by Maciej W. Rozycki's avatar Maciej W. Rozycki Committed by Ralf Baechle
Browse files

MIPS: tlb-r3k: Move CP0.Wired register initialisation to `tlb_init' 



Move the initialisation of the CP0.Wired register implemented by Toshiba
TX3922 and TX3927 processors from `tx39_cache_init' to `tlb_init' where
it belongs, correcting code structure and making sure initialisation
does not rely on `tx39_cache_init' being called before `tlb_init' to
work correctly.

Make `r3k_have_wired_reg' static as it's no longer externally referred
to; remove a stale declaration too.

Signed-off-by: default avatarMaciej W. Rozycki <macro@linux-mips.org>
Cc: James Hogan <james.hogan@imgtec.com>
Cc: linux-mips@linux-mips.org
Patchwork: https://patchwork.linux-mips.org/patch/10195/


Signed-off-by: default avatarRalf Baechle <ralf@linux-mips.org>
parent dbfbf60f

arch/mips/lib/r3k_dump_tlb.c

+0 −2
Original line number Diff line number Diff line
@@ -14,8 +14,6 @@ 
#include <asm/pgtable.h>

#include <asm/tlbdebug.h>



extern int r3k_have_wired_reg;	/* defined in tlb-r3k.c */



static void dump_tlb(int first, int last)

{

	int	i;

arch/mips/mm/c-tx39.c

+0 −4
Original line number Diff line number Diff line
@@ -28,8 +28,6 @@ static unsigned long icache_size, dcache_size; /* Size in bytes */ 


#include <asm/r4kcache.h>



extern int r3k_have_wired_reg;	/* in r3k-tlb.c */



/* This sequence is required to ensure icache is disabled immediately */

#define TX39_STOP_STREAMING() \

__asm__ __volatile__( \
@@ -383,8 +381,6 @@ void tx39_cache_init(void) 
	case CPU_TX3927:

	default:

		/* TX39/H2,H3 core (writeback 2way-set-associative cache) */

		r3k_have_wired_reg = 1;

		write_c0_wired(0);	/* set 8 on reset... */

		/* board-dependent init code may set WBON */



		__flush_cache_vmap	= tx39__flush_cache_vmap;

arch/mips/mm/tlb-r3k.c

+8 −1
Original line number Diff line number Diff line
@@ -36,7 +36,7 @@ extern void build_tlb_refill_handler(void); 
		"nop\n\t"		\

		".set	pop\n\t")



int r3k_have_wired_reg;		/* should be in cpu_data? */

static int r3k_have_wired_reg;			/* Should be in cpu_data? */



/* TLB operations. */

static void local_flush_tlb_from(int entry)
@@ -280,6 +280,13 @@ void add_wired_entry(unsigned long entrylo0, unsigned long entrylo1, 


void tlb_init(void)

{

	switch (current_cpu_type()) {

	case CPU_TX3922:

	case CPU_TX3927:

		r3k_have_wired_reg = 1;

		write_c0_wired(0);		/* Set to 8 on reset... */

		break;

	}

	local_flush_tlb_from(0);

	build_tlb_refill_handler();

}