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Commit 993dd17e authored by Kanigeri, Hari's avatar Kanigeri, Hari Committed by Hiroshi DOYU
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omap iommu: update irq mask to be specific about twl and tlb 



Revise the IRQ mask definitions to handle the  MMU faults related
to TWL fault as well as TLB miss fault.

Signed-off-by: default avatarHari Kanigeri <h-kanigeri2@ti.com>
Signed-off-by: default avatarHiroshi Doyu <Hiroshi.DOYU@nokia.com>
parent 12493359

arch/arm/mach-omap2/iommu2.c

+8 −4
Original line number Original line Diff line number Diff line
@@ -44,9 +44,13 @@ 
#define MMU_IRQ_EMUMISS		(1 << 2)

#define MMU_IRQ_EMUMISS		(1 << 2)

#define MMU_IRQ_TRANSLATIONFAULT	(1 << 1)

#define MMU_IRQ_TRANSLATIONFAULT	(1 << 1)

#define MMU_IRQ_TLBMISS		(1 << 0)

#define MMU_IRQ_TLBMISS		(1 << 0)



#define __MMU_IRQ_FAULT		\

	(MMU_IRQ_MULTIHITFAULT | MMU_IRQ_EMUMISS | MMU_IRQ_TRANSLATIONFAULT)

#define MMU_IRQ_MASK		\

#define MMU_IRQ_MASK		\

	(MMU_IRQ_MULTIHITFAULT | MMU_IRQ_TABLEWALKFAULT | MMU_IRQ_EMUMISS | \

	(__MMU_IRQ_FAULT | MMU_IRQ_TABLEWALKFAULT | MMU_IRQ_TLBMISS)

	 MMU_IRQ_TRANSLATIONFAULT)

#define MMU_IRQ_TWL_MASK	(__MMU_IRQ_FAULT | MMU_IRQ_TABLEWALKFAULT)

#define MMU_IRQ_TLB_MISS_MASK	(__MMU_IRQ_FAULT | MMU_IRQ_TLBMISS)





/* MMU_CNTL */

/* MMU_CNTL */

#define MMU_CNTL_SHIFT		1

#define MMU_CNTL_SHIFT		1
@@ -96,7 +100,7 @@ static int omap2_iommu_enable(struct iommu *obj) 
	l |= (MMU_SYS_IDLE_SMART | MMU_SYS_AUTOIDLE);

	l |= (MMU_SYS_IDLE_SMART | MMU_SYS_AUTOIDLE);

	iommu_write_reg(obj, l, MMU_SYSCONFIG);

	iommu_write_reg(obj, l, MMU_SYSCONFIG);





	iommu_write_reg(obj, MMU_IRQ_MASK, MMU_IRQENABLE);

	iommu_write_reg(obj, MMU_IRQ_TWL_MASK, MMU_IRQENABLE);

	iommu_write_reg(obj, pa, MMU_TTB);

	iommu_write_reg(obj, pa, MMU_TTB);





	l = iommu_read_reg(obj, MMU_CNTL);

	l = iommu_read_reg(obj, MMU_CNTL);