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Commit 985a8bc7 authored by qctecmdr's avatar qctecmdr Committed by Gerrit - the friendly Code Review server
Browse files

Merge "msm: kgsl: Remove the CPU pagetable path"

parents 8bde9d7a fc073bbf

Documentation/devicetree/bindings/gpu/adreno-iommu.txt

+0 −12
Original line number Diff line number Diff line
@@ -25,17 +25,11 @@ Required properties: 
		  is a separate aperture for CP to program context banks.



Optional properties:

- qcom,micro-mmu-control : Some targets provide an implementation defined

		  register for blocking translation requests during GPU side

		  programming.  This property specifies the offset of this

		  register within the iommu register space.

- qcom,retention :  A boolean specifying if retention is supported on this target

- qcom,global_pt :  A boolean specifying if global pagetable should be used.

		  When not set we use per process pagetables

- qcom,hyp_secure_alloc : A bool specifying if the hypervisor is used on this target

		  for secure buffer allocation

- qcom,secure_align_mask: A mask for determining how secure buffers need to

		  be aligned



- List of sub nodes, one for each of the translation context banks supported.

  The driver uses the names of these nodes to determine how they are used,
@@ -53,11 +47,6 @@ Optional properties: 
		   defined in iommu device tree. On targets where the msm iommu

		   driver is used rather than the arm smmu driver, this property

		   may be absent.

	- qcom,gpu-offset :  Offset into the GPU register space for accessing

		   this context bank. On some targets the iommu registers are not

		   part of the GPU's register space, and a separate register aperture

		   is used. Otherwise the same register offsets may be used for CPU

		   or GPU side programming.



Example:
@@ -78,7 +67,6 @@ msm_iommu: qcom,kgsl-iommu@2ca0000 { 
		compatible = "qcom,smmu-kgsl-cb";

		iommus = <&kgsl_smmu 0>,

			 <&kgsl_smmu 1>;

		qcom,gpu-offset = <0xa8000>;

	};



	gfx3d_secure: gfx3d_secure {

drivers/gpu/msm/Makefile

+0 −3
Original line number Diff line number Diff line
@@ -32,14 +32,11 @@ msm_adreno-y += \ 
	adreno_coresight.o \

	adreno_trace.o \

	adreno_a3xx.o \

	adreno_a4xx.o \

	adreno_a5xx.o \

	adreno_a6xx.o \

	adreno_a3xx_snapshot.o \

	adreno_a4xx_snapshot.o \

	adreno_a5xx_snapshot.o \

	adreno_a6xx_snapshot.o \

	adreno_a4xx_preempt.o \

	adreno_a5xx_preempt.o \

	adreno_a6xx_preempt.o \

	adreno_a6xx_gmu.o \

drivers/gpu/msm/a4xx_reg.h

deleted100644 → 0
+0 −839

File deleted.

Preview size limit exceeded, changes collapsed.

drivers/gpu/msm/adreno-gpulist.h

+8 −118
Original line number Diff line number Diff line 
/* SPDX-License-Identifier: GPL-2.0 */

/* SPDX-License-Identifier: GPL-2.0-only */

/*

 * Copyright (c) 2002,2007-2019, The Linux Foundation. All rights reserved.

 */
@@ -51,12 +51,7 @@ static const struct adreno_gpu_core adreno_gpulist[] = { 
		.major = 0,

		.minor = 5,

		.patchid = ANY_ID,

		.features = ADRENO_SOFT_FAULT_DETECT,

		.pm4fw_name = "a420_pm4.fw",

		.pfpfw_name = "a420_pfp.fw",

		.gpudev = &adreno_a4xx_gpudev,

		.gmem_size = SZ_256K,

		.busy_mask = 0x7FFFFFFE,

		.features = ADRENO_DEPRECATED,

	},

	{

		.gpurev = ADRENO_REV_A420,
@@ -64,20 +59,7 @@ static const struct adreno_gpu_core adreno_gpulist[] = { 
		.major = 2,

		.minor = 0,

		.patchid = ANY_ID,

		.features = ADRENO_USES_OCMEM | ADRENO_WARM_START |

			ADRENO_USE_BOOTSTRAP | ADRENO_SOFT_FAULT_DETECT,

		.pm4fw_name = "a420_pm4.fw",

		.pfpfw_name = "a420_pfp.fw",

		.gpudev = &adreno_a4xx_gpudev,

		.gmem_size = (SZ_1M + SZ_512K),

		.pm4_jt_idx = 0x901,

		.pm4_jt_addr = 0x300,

		.pfp_jt_idx = 0x401,

		.pfp_jt_addr = 0x400,

		.pm4_bstrp_size = 0x06,

		.pfp_bstrp_size = 0x28,

		.pfp_bstrp_ver = 0x4ff083,

		.busy_mask = 0x7FFFFFFE,

		.features = ADRENO_DEPRECATED,

	},

	{

		.gpurev = ADRENO_REV_A430,
@@ -85,25 +67,7 @@ static const struct adreno_gpu_core adreno_gpulist[] = { 
		.major = 3,

		.minor = 0,

		.patchid = ANY_ID,

		.features = ADRENO_USES_OCMEM  | ADRENO_WARM_START |

			ADRENO_USE_BOOTSTRAP | ADRENO_SPTP_PC | ADRENO_PPD |

			ADRENO_CONTENT_PROTECTION | ADRENO_PREEMPTION |

			ADRENO_SOFT_FAULT_DETECT,

		.pm4fw_name = "a420_pm4.fw",

		.pfpfw_name = "a420_pfp.fw",

		.gpudev = &adreno_a4xx_gpudev,

		.gmem_size = (SZ_1M + SZ_512K),

		.pm4_jt_idx = 0x901,

		.pm4_jt_addr = 0x300,

		.pfp_jt_idx = 0x401,

		.pfp_jt_addr = 0x400,

		.pm4_bstrp_size = 0x06,

		.pfp_bstrp_size = 0x28,

		.pfp_bstrp_ver = 0x4ff083,

		.shader_offset = 0x20000,

		.shader_size = 0x10000,

		.num_protected_regs = 0x18,

		.busy_mask = 0x7FFFFFFE,

		.features = ADRENO_DEPRECATED,

	},

	{

		.gpurev = ADRENO_REV_A418,
@@ -111,24 +75,7 @@ static const struct adreno_gpu_core adreno_gpulist[] = { 
		.major = 1,

		.minor = 8,

		.patchid = ANY_ID,

		.features = ADRENO_USES_OCMEM  | ADRENO_WARM_START |

			ADRENO_USE_BOOTSTRAP | ADRENO_SPTP_PC |

			ADRENO_SOFT_FAULT_DETECT,

		.pm4fw_name = "a420_pm4.fw",

		.pfpfw_name = "a420_pfp.fw",

		.gpudev = &adreno_a4xx_gpudev,

		.gmem_size = (SZ_512K),

		.pm4_jt_idx = 0x901,

		.pm4_jt_addr = 0x300,

		.pfp_jt_idx = 0x401,

		.pfp_jt_addr = 0x400,

		.pm4_bstrp_size = 0x06,

		.pfp_bstrp_size = 0x28,

		.pfp_bstrp_ver = 0x4ff083,

		.shader_offset = 0x20000, /* SP and TP addresses */

		.shader_size = 0x10000,

		.num_protected_regs = 0x18,

		.busy_mask = 0x7FFFFFFE,

		.features = ADRENO_DEPRECATED,

	},

	{

		.gpurev = ADRENO_REV_A530,
@@ -136,12 +83,7 @@ static const struct adreno_gpu_core adreno_gpulist[] = { 
		.major = 3,

		.minor = 0,

		.patchid = 0,

		.pm4fw_name = "a530v1_pm4.fw",

		.pfpfw_name = "a530v1_pfp.fw",

		.gpudev = &adreno_a5xx_gpudev,

		.gmem_size = SZ_1M,

		.num_protected_regs = 0x20,

		.busy_mask = 0xFFFFFFFE,

		.features = ADRENO_DEPRECATED,

	},

	{

		.gpurev = ADRENO_REV_A530,
@@ -242,21 +184,7 @@ static const struct adreno_gpu_core adreno_gpulist[] = { 
		.major = 4,

		.minor = 0,

		.patchid = 0,

		.features = ADRENO_PREEMPTION | ADRENO_64BIT |

			ADRENO_CONTENT_PROTECTION |

			ADRENO_GPMU | ADRENO_SPTP_PC,

		.pm4fw_name = "a530_pm4.fw",

		.pfpfw_name = "a530_pfp.fw",

		.zap_name = "a540_zap",

		.gpudev = &adreno_a5xx_gpudev,

		.gmem_size = SZ_1M,

		.num_protected_regs = 0x20,

		.busy_mask = 0xFFFFFFFE,

		.gpmufw_name = "a540_gpmu.fw2",

		.gpmu_major = 3,

		.gpmu_minor = 0,

		.gpmu_tsens = 0x000C000D,

		.max_power = 5448,

		.features = ADRENO_DEPRECATED,

	},

	{

		.gpurev = ADRENO_REV_A540,
@@ -318,21 +246,7 @@ static const struct adreno_gpu_core adreno_gpulist[] = { 
		.major = 3,

		.minor = 0,

		.patchid = 0,

		.features = ADRENO_64BIT | ADRENO_RPMH |

			ADRENO_GPMU | ADRENO_CONTENT_PROTECTION | ADRENO_LM,

		.sqefw_name = "a630_sqe.fw",

		.zap_name = "a630_zap",

		.gpudev = &adreno_a6xx_gpudev,

		.gmem_size = SZ_1M,

		.num_protected_regs = 0x20,

		.busy_mask = 0xFFFFFFFE,

		.gpmufw_name = "a630_gmu.bin",

		.gpmu_major = 0x1,

		.gpmu_minor = 0x003,

		.gpmu_tsens = 0x000C000D,

		.max_power = 5448,

		.prim_fifo_threshold = 0x0018000,

		.pdc_address_offset = 0x00030080,

		.features = ADRENO_DEPRECATED,

	},

	{

		.gpurev = ADRENO_REV_A630,
@@ -399,30 +313,6 @@ static const struct adreno_gpu_core adreno_gpulist[] = { 
		.prim_fifo_threshold = 0x0018000,

		.pdc_address_offset = 0x00030090,

	},

	{

		.gpurev = ADRENO_REV_A640,

		.core = 6,

		.major = 4,

		.minor = 0,

		.patchid = 0,

		.features = ADRENO_64BIT | ADRENO_RPMH | ADRENO_GPMU |

			ADRENO_CONTENT_PROTECTION | ADRENO_IOCOHERENT |

			ADRENO_IFPC,

		.sqefw_name = "a630_sqe.fw",

		.zap_name = "a640_zap",

		.gpudev = &adreno_a6xx_gpudev,

		.gmem_size = SZ_1M, //Verified 1MB

		.num_protected_regs = 0x20,

		.busy_mask = 0xFFFFFFFE,

		.gpmufw_name = "a640_gmu.bin",

		.gpmu_major = 0x2,

		.gpmu_minor = 0x000,

		.gpmu_tsens = 0x000C000D,

		.max_power = 5448,

		.va_padding = SZ_64K,

		.prim_fifo_threshold = 0x00200000,

		.pdc_address_offset = 0x00030090,

	},

	{

		.gpurev = ADRENO_REV_A640,

		.core = 6,

drivers/gpu/msm/adreno.c

+31 −111
Original line number Diff line number Diff line
@@ -72,7 +72,7 @@ static struct adreno_device device_3d0 = { 
	.long_ib_detect = 1,

	.input_work = __WORK_INITIALIZER(device_3d0.input_work,

		adreno_input_work),

	.pwrctrl_flag = BIT(ADRENO_SPTP_PC_CTRL) | BIT(ADRENO_PPD_CTRL) |

	.pwrctrl_flag = BIT(ADRENO_SPTP_PC_CTRL) |

		BIT(ADRENO_LM_CTRL) | BIT(ADRENO_HWCG_CTRL) |

		BIT(ADRENO_THROTTLING_CTRL),

	.profile.enabled = false,
@@ -499,17 +499,6 @@ static int _soft_reset(struct adreno_device *adreno_dev) 
	struct adreno_gpudev *gpudev  = ADRENO_GPU_DEVICE(adreno_dev);

	unsigned int reg;



	/*

	 * On a530 v1 RBBM cannot be reset in soft reset.

	 * Reset all blocks except RBBM for a530v1.

	 */

	if (adreno_is_a530v1(adreno_dev)) {

		adreno_writereg(adreno_dev, ADRENO_REG_RBBM_BLOCK_SW_RESET_CMD,

						 0xFFDFFC0);

		adreno_writereg(adreno_dev, ADRENO_REG_RBBM_BLOCK_SW_RESET_CMD2,

						0x1FFFFFFF);

	} else {



	adreno_writereg(adreno_dev, ADRENO_REG_RBBM_SW_RESET_CMD, 1);

	/*

	 * Do a dummy read to get a brief read cycle delay for the
@@ -517,7 +506,6 @@ static int _soft_reset(struct adreno_device *adreno_dev) 
	 */

	adreno_readreg(adreno_dev, ADRENO_REG_RBBM_SW_RESET_CMD, &reg);

	adreno_writereg(adreno_dev, ADRENO_REG_RBBM_SW_RESET_CMD, 0);

	}



	/* The SP/TP regulator gets turned off after a soft reset */
@@ -782,9 +770,9 @@ static void adreno_update_soc_hw_revision_quirks( 
	}

}



static void

adreno_identify_gpu(struct adreno_device *adreno_dev)

static int adreno_identify_gpu(struct adreno_device *adreno_dev)

{

	struct kgsl_device *device = KGSL_DEVICE(adreno_dev);

	const struct adreno_reg_offsets *reg_offsets;

	struct adreno_gpudev *gpudev;

	int i;
@@ -792,10 +780,23 @@ adreno_identify_gpu(struct adreno_device *adreno_dev) 
	adreno_dev->gpucore = _get_gpu_core(adreno_dev->chipid);



	if (adreno_dev->gpucore == NULL) {

		dev_crit(KGSL_DEVICE(adreno_dev)->dev,

		dev_crit(&device->pdev->dev,

			"Unknown GPU chip ID %8.8X\n", adreno_dev->chipid);

		BUG();

		return;

		return -ENODEV;

	}



	/*

	 * Identify non-longer supported targets and spins and print a helpful

	 * message

	 */

	if (adreno_dev->gpucore->features & ADRENO_DEPRECATED) {

		dev_err(&device->pdev->dev,

			"Support for GPU %d.%d.%d.%d has been deprecated\n",

			adreno_dev->gpucore->core,

			adreno_dev->gpucore->major,

			adreno_dev->gpucore->minor,

			adreno_dev->gpucore->patchid);

		return -ENODEV;

	}



	/*
@@ -821,6 +822,8 @@ adreno_identify_gpu(struct adreno_device *adreno_dev) 
	/* Do target specific identification */

	if (gpudev->platform_setup != NULL)

		gpudev->platform_setup(adreno_dev);



	return 0;

}



static const struct platform_device_id adreno_id_table[] = {
@@ -1129,49 +1132,6 @@ static int adreno_of_get_power(struct adreno_device *adreno_dev, 
	return 0;

}



#ifdef CONFIG_QCOM_OCMEM

static int

adreno_ocmem_malloc(struct adreno_device *adreno_dev)

{

	if (!ADRENO_FEATURE(adreno_dev, ADRENO_USES_OCMEM))

		return 0;



	if (adreno_dev->ocmem_hdl == NULL) {

		adreno_dev->ocmem_hdl =

			ocmem_allocate(OCMEM_GRAPHICS, adreno_dev->gmem_size);

		if (IS_ERR_OR_NULL(adreno_dev->ocmem_hdl)) {

			adreno_dev->ocmem_hdl = NULL;

			return -ENOMEM;

		}



		adreno_dev->gmem_size = adreno_dev->ocmem_hdl->len;

		adreno_dev->gmem_base = adreno_dev->ocmem_hdl->addr;

	}



	return 0;

}



static void

adreno_ocmem_free(struct adreno_device *adreno_dev)

{

	if (adreno_dev->ocmem_hdl != NULL) {

		ocmem_free(OCMEM_GRAPHICS, adreno_dev->ocmem_hdl);

		adreno_dev->ocmem_hdl = NULL;

	}

}

#else

static int

adreno_ocmem_malloc(struct adreno_device *adreno_dev)

{

	return 0;

}



static void

adreno_ocmem_free(struct adreno_device *adreno_dev)

{

}

#endif



static void adreno_cx_dbgc_probe(struct kgsl_device *device)

{

	struct adreno_device *adreno_dev = ADRENO_DEVICE(device);
@@ -1325,7 +1285,8 @@ static int adreno_probe(struct platform_device *pdev) 
	adreno_update_soc_hw_revision_quirks(adreno_dev, pdev);



	/* Get the chip ID from the DT and set up target specific parameters */

	adreno_identify_gpu(adreno_dev);

	if (adreno_identify_gpu(adreno_dev))

		return -ENODEV;



	status = adreno_of_get_power(adreno_dev, pdev);

	if (status) {
@@ -1352,14 +1313,6 @@ static int adreno_probe(struct platform_device *pdev) 
	if (adreno_support_64bit(adreno_dev))

		device->mmu.features |= KGSL_MMU_64BIT;



	/* Default to 4K alignment (in other words, no additional padding) */

	device->mmu.va_padding = PAGE_SIZE;



	if (adreno_dev->gpucore->va_padding) {

		device->mmu.features |= KGSL_MMU_PAD_VA;

		device->mmu.va_padding = adreno_dev->gpucore->va_padding;

	}



	status = kgsl_device_platform_probe(device);

	if (status) {

		device->pdev = NULL;
@@ -1641,9 +1594,7 @@ static int adreno_init(struct kgsl_device *device) 
			return ret;

	}



	ret = adreno_iommu_init(adreno_dev);

	if (ret)

		return ret;

	 adreno_iommu_init(adreno_dev);



	adreno_perfcounter_init(adreno_dev);

	adreno_fault_detect_init(adreno_dev);
@@ -1737,9 +1688,6 @@ static void _set_secvid(struct kgsl_device *device) 


	/* Program GPU contect protection init values */

	if (device->mmu.secured && !set) {

		if (adreno_is_a4xx(adreno_dev))

			adreno_writereg(adreno_dev,

				ADRENO_REG_RBBM_SECVID_TRUST_CONFIG, 0x2);

		adreno_writereg(adreno_dev,

				ADRENO_REG_RBBM_SECVID_TSB_CONTROL, 0x0);
@@ -1866,35 +1814,12 @@ static int _adreno_start(struct adreno_device *adreno_dev) 
		_soft_reset(adreno_dev);





	if (adreno_is_a640v1(adreno_dev)) {

		unsigned long start = jiffies;



		if (scm_is_call_available(SCM_SVC_MP, CP_SMMU_APERTURE_ID)) {

			ret = kgsl_program_smmu_aperture();

			/* Log it if it takes more than 2 seconds */

			if (((jiffies - start) / HZ) > 2)

				dev_err(device->dev, "scm call took too long to finish on a640v1: %lu seconds\n",

					((jiffies - start) / HZ));

			if (ret) {

				dev_err(device->dev, "SMMU aperture programming call failed with error %d\n",

					ret);

				goto error_pwr_off;

			}

		}

	}



	adreno_ringbuffer_set_global(adreno_dev, 0);



	status = kgsl_mmu_start(device);

	if (status)

		goto error_boot_oob_clear;



	status = adreno_ocmem_malloc(adreno_dev);

	if (status) {

		dev_err(device->dev, "OCMEM malloc failed\n");

		goto error_mmu_off;

	}



	/* Send OOB request to turn on the GX */

	status = gmu_core_dev_oob_set(device, oob_gpu);

	if (status)
@@ -2070,7 +1995,7 @@ static int _adreno_start(struct adreno_device *adreno_dev) 
	/* Clear FSR here in case it is set from a previous pagefault */

	kgsl_mmu_clear_fsr(&device->mmu);



	status = adreno_ringbuffer_start(adreno_dev, ADRENO_START_COLD);

	status = adreno_ringbuffer_start(adreno_dev);

	if (status)

		goto error_oob_clear;
@@ -2177,8 +2102,6 @@ static int adreno_stop(struct kgsl_device *device) 


	adreno_irqctrl(adreno_dev, 0);



	adreno_ocmem_free(adreno_dev);



	adreno_llc_deactivate_slice(adreno_dev->gpu_llc_slice);

	adreno_llc_deactivate_slice(adreno_dev->gpuhtw_llc_slice);
@@ -2825,10 +2748,7 @@ int adreno_soft_reset(struct kgsl_device *device) 
	 * otherwise do a full ringbuffer restart

	 */



	if (ADRENO_FEATURE(adreno_dev, ADRENO_WARM_START))

		ret = adreno_ringbuffer_start(adreno_dev, ADRENO_START_WARM);

	else

		ret = adreno_ringbuffer_start(adreno_dev, ADRENO_START_COLD);

	ret = adreno_ringbuffer_start(adreno_dev);

	if (ret == 0) {

		device->reset_counter++;

		set_bit(ADRENO_DEVICE_STARTED, &adreno_dev->priv);