Donate to e Foundation | Murena handsets with /e/OS | Own a part of Murena! Learn more

Commit 96987ded authored by Tomasz Figa's avatar Tomasz Figa
Browse files

clk: samsung: exynos5250: Fix parents of gate clocks from MFC domain 



This patch adds mout_aclk333_sub mux clock and updates gate clocks from
MFC domain to have it as their parent as specified in SoC documentation.

Signed-off-by: default avatarTomasz Figa <t.figa@samsung.com>
Signed-off-by: default avatarKyungmin Park <kyungmin.park@samsung.com>
Tested-by: default avatarTomasz Figa <t.figa@samsung.com>
parent bfeb9f27

drivers/clk/samsung/clk-exynos5250.c

+5 −3
Original line number Diff line number Diff line
@@ -199,6 +199,7 @@ PNAME(mout_aclk166_p) = { "mout_cpll", "mout_mpll_user" }; 
PNAME(mout_aclk200_p)	= { "mout_mpll_user", "mout_bpll_user" };

PNAME(mout_aclk200_sub_p) = { "fin_pll", "div_aclk200" };

PNAME(mout_aclk266_sub_p) = { "fin_pll", "div_aclk266" };

PNAME(mout_aclk333_sub_p) = { "fin_pll", "div_aclk333" };

PNAME(mout_hdmi_p)	= { "div_hdmi_pixel", "sclk_hdmiphy" };

PNAME(mout_usb3_p)	= { "mout_mpll_user", "mout_cpll" };

PNAME(mout_group1_p)	= { "fin_pll", "fin_pll", "sclk_hdmi27m",
@@ -284,6 +285,7 @@ static struct samsung_mux_clock exynos5250_mux_clks[] __initdata = { 


	MUX(none, "mout_aclk200_disp1_sub", mout_aclk200_sub_p, SRC_TOP3, 4, 1),

	MUX(none, "mout_aclk266_gscl_sub", mout_aclk266_sub_p, SRC_TOP3, 8, 1),

	MUX(none, "mout_aclk333_sub", mout_aclk333_sub_p, SRC_TOP3, 24, 1),



	MUX(none, "mout_cam_bayer", mout_group1_p, SRC_GSCL, 12, 4),

	MUX(none, "mout_cam0", mout_group1_p, SRC_GSCL, 16, 4),
@@ -520,9 +522,9 @@ static struct samsung_gate_clock exynos5250_gate_clks[] __initdata = { 
	GATE(mixer, "mixer", "mout_aclk200_disp1_sub", GATE_IP_DISP1, 5, 0, 0),

	GATE(hdmi, "hdmi", "mout_aclk200_disp1_sub", GATE_IP_DISP1, 6, 0, 0),



	GATE(mfc, "mfc", "div_aclk333", GATE_IP_MFC, 0, 0, 0),

	GATE(smmu_mfcr, "smmu_mfcr", "div_aclk333", GATE_IP_MFC, 1, 0, 0),

	GATE(smmu_mfcl, "smmu_mfcl", "div_aclk333", GATE_IP_MFC, 2, 0, 0),

	GATE(mfc, "mfc", "mout_aclk333_sub", GATE_IP_MFC, 0, 0, 0),

	GATE(smmu_mfcr, "smmu_mfcr", "mout_aclk333_sub", GATE_IP_MFC, 1, 0, 0),

	GATE(smmu_mfcl, "smmu_mfcl", "mout_aclk333_sub", GATE_IP_MFC, 2, 0, 0),



	GATE(rotator, "rotator", "div_aclk266", GATE_IP_GEN, 1, 0, 0),

	GATE(jpeg, "jpeg", "div_aclk166", GATE_IP_GEN, 2, 0, 0),