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Commit bfeb9f27 authored by Tomasz Figa's avatar Tomasz Figa
Browse files

clk: samsung: exynos5250: Correct parent list of audio muxes 



According to SoC documentation, input 5 of mout_audio muxes is connected
to xxti (named fin_pll in the driver). This patch corrects defined
parent arrays to match SoC documentation.

Signed-off-by: default avatarTomasz Figa <t.figa@samsung.com>
Signed-off-by: default avatarKyungmin Park <kyungmin.park@samsung.com>
Tested-by: default avatarTomasz Figa <t.figa@samsung.com>
parent 256dd646

drivers/clk/samsung/clk-exynos5250.c

+3 −3
Original line number Diff line number Diff line
@@ -208,19 +208,19 @@ PNAME(mout_group1_p) = { "fin_pll", "fin_pll", "sclk_hdmi27m", 
				"none", "none", "none",

				"none" };

PNAME(mout_audio0_p)	= { "cdclk0", "fin_pll", "sclk_hdmi27m", "sclk_dptxphy",

				"sclk_uhostphy", "sclk_hdmiphy",

				"sclk_uhostphy", "fin_pll",

				"mout_mpll_user", "mout_epll", "mout_vpll",

				"mout_cpll", "none", "none",

				"none", "none", "none",

				"none" };

PNAME(mout_audio1_p)	= { "cdclk1", "fin_pll", "sclk_hdmi27m", "sclk_dptxphy",

				"sclk_uhostphy", "sclk_hdmiphy",

				"sclk_uhostphy", "fin_pll",

				"mout_mpll_user", "mout_epll", "mout_vpll",

				"mout_cpll", "none", "none",

				"none", "none", "none",

				"none" };

PNAME(mout_audio2_p)	= { "cdclk2", "fin_pll", "sclk_hdmi27m", "sclk_dptxphy",

				"sclk_uhostphy", "sclk_hdmiphy",

				"sclk_uhostphy", "fin_pll",

				"mout_mpll_user", "mout_epll", "mout_vpll",

				"mout_cpll", "none", "none",

				"none", "none", "none",