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Commit 907fce09 authored by Gabriele Paoloni's avatar Gabriele Paoloni Committed by Bjorn Helgaas
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PCI: designware: Make "num-lanes" an optional DT property 



Currently "num-lanes" is read in dw_pcie_host_init(), but it is only used
if we call dw_pcie_setup_rc() while bringing up the link.  If the link has
already been brought up by firmware, we need not call dw_pcie_setup_rc(),
and "num-lanes" is unnecessary.

Only complain about "num-lanes" if we actually need it and we didn't find a
valid value.

[bhelgaas: changelog]
Signed-off-by: default avatarGabriele Paoloni <gabriele.paoloni@huawei.com>
Signed-off-by: default avatarBjorn Helgaas <bhelgaas@google.com>
parent b6b18f58

Documentation/devicetree/bindings/pci/designware-pcie.txt

+2 −1
Original line number Original line Diff line number Diff line
@@ -14,7 +14,6 @@ Required properties: 
- interrupt-map-mask and interrupt-map: standard PCI properties

- interrupt-map-mask and interrupt-map: standard PCI properties

	to define the mapping of the PCIe interface to interrupt

	to define the mapping of the PCIe interface to interrupt

	numbers.

	numbers.

- num-lanes: number of lanes to use

- clocks: Must contain an entry for each entry in clock-names.

- clocks: Must contain an entry for each entry in clock-names.

	See ../clocks/clock-bindings.txt for details.

	See ../clocks/clock-bindings.txt for details.

- clock-names: Must include the following entries:

- clock-names: Must include the following entries:
@@ -22,6 +21,8 @@ Required properties: 
	- "pcie_bus"

	- "pcie_bus"





Optional properties:

Optional properties:

- num-lanes: number of lanes to use (this property should be specified unless

  the link is brought already up in BIOS)

- reset-gpio: gpio pin number of power good signal

- reset-gpio: gpio pin number of power good signal

- bus-range: PCI bus numbers covered (it is recommended for new devicetrees to

- bus-range: PCI bus numbers covered (it is recommended for new devicetrees to

  specify this property, to keep backwards compatibility a range of 0x00-0xff

  specify this property, to keep backwards compatibility a range of 0x00-0xff

drivers/pci/host/pcie-designware.c

+6 −4
Original line number Original line Diff line number Diff line
@@ -534,10 +534,9 @@ int dw_pcie_host_init(struct pcie_port *pp) 
		}

		}

	}

	}





	if (of_property_read_u32(np, "num-lanes", &pp->lanes)) {

	ret = of_property_read_u32(np, "num-lanes", &pp->lanes);

		dev_err(pp->dev, "Failed to parse the number of lanes\n");

	if (ret)

		return -EINVAL;

		pp->lanes = 0;

	}





	if (IS_ENABLED(CONFIG_PCI_MSI)) {

	if (IS_ENABLED(CONFIG_PCI_MSI)) {

		if (!pp->ops->msi_host_init) {

		if (!pp->ops->msi_host_init) {
@@ -814,6 +813,9 @@ void dw_pcie_setup_rc(struct pcie_port *pp) 
	case 8:

	case 8:

		val |= PORT_LINK_MODE_8_LANES;

		val |= PORT_LINK_MODE_8_LANES;

		break;

		break;

	default:

		dev_err(pp->dev, "num-lanes %u: invalid value\n", pp->lanes);

		return;

	}

	}

	dw_pcie_writel_rc(pp, val, PCIE_PORT_LINK_CONTROL);

	dw_pcie_writel_rc(pp, val, PCIE_PORT_LINK_CONTROL);