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Commit b6b18f58 authored by Gabriele Paoloni's avatar Gabriele Paoloni Committed by Bjorn Helgaas
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PCI: designware: Require config accesses to be naturally aligned 



Add sanity checks on "addr" input parameter in dw_pcie_cfg_read() and
dw_pcie_cfg_write().  These checks make sure that accesses are aligned on
their size, e.g., a 4-byte config access is aligned on a 4-byte boundary.

[bhelgaas: changelog, set *val = 0 in failure case]
Signed-off-by: default avatarGabriele Paoloni <gabriele.paoloni@huawei.com>
Signed-off-by: default avatarBjorn Helgaas <bhelgaas@google.com>
Acked-by: default avatarPratyush Anand <pratyush.anand@gmail.com>
parent 4c45852f

drivers/pci/host/pcie-designware.c

+8 −0
Original line number Diff line number Diff line
@@ -82,6 +82,11 @@ static inline struct pcie_port *sys_to_pcie(struct pci_sys_data *sys) 


int dw_pcie_cfg_read(void __iomem *addr, int size, u32 *val)

{

	if ((uintptr_t)addr & (size - 1)) {

		*val = 0;

		return PCIBIOS_BAD_REGISTER_NUMBER;

	}



	if (size == 4)

		*val = readl(addr);

	else if (size == 2)
@@ -98,6 +103,9 @@ int dw_pcie_cfg_read(void __iomem *addr, int size, u32 *val) 


int dw_pcie_cfg_write(void __iomem *addr, int size, u32 val)

{

	if ((uintptr_t)addr & (size - 1))

		return PCIBIOS_BAD_REGISTER_NUMBER;



	if (size == 4)

		writel(val, addr);

	else if (size == 2)