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Commit 883cc17c authored by Gabriele Paoloni's avatar Gabriele Paoloni Committed by Bjorn Helgaas
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PCI: designware: Move calculation of bus addresses to DRA7xx 



Commit f4c55c5a ("PCI: designware: Program ATU with untranslated
address") added the calculation of PCI bus addresses in pcie-designware.c,
storing them in new fields added in struct pcie_port.  This calculation is
done for every DesignWare user even though it only applies to DRA7xx.

Move the calculation of the bus addresses to the DRA7xx driver to allow the
rework of DesignWare to use the new DT parsing API.

Signed-off-by: default avatarGabriele Paoloni <gabriele.paoloni@huawei.com>
Signed-off-by: default avatarZhou Wang <wangzhou1@hisilicon.com>
Signed-off-by: default avatarBjorn Helgaas <bhelgaas@google.com>
Acked-by: default avatarPratyush Anand <pratyush.anand@gmail.com>
parent 907fce09

drivers/pci/host/pci-dra7xx.c

+7 −0
Original line number Original line Diff line number Diff line
@@ -62,6 +62,7 @@ 




#define	PCIECTRL_DRA7XX_CONF_PHY_CS			0x010C

#define	PCIECTRL_DRA7XX_CONF_PHY_CS			0x010C

#define	LINK_UP						BIT(16)

#define	LINK_UP						BIT(16)

#define	DRA7XX_CPU_TO_BUS_ADDR				0x0FFFFFFF





struct dra7xx_pcie {

struct dra7xx_pcie {

	void __iomem		*base;

	void __iomem		*base;
@@ -151,6 +152,12 @@ static void dra7xx_pcie_enable_interrupts(struct pcie_port *pp) 
static void dra7xx_pcie_host_init(struct pcie_port *pp)

static void dra7xx_pcie_host_init(struct pcie_port *pp)

{

{

	dw_pcie_setup_rc(pp);

	dw_pcie_setup_rc(pp);



	pp->io_mod_base &= DRA7XX_CPU_TO_BUS_ADDR;

	pp->mem_mod_base &= DRA7XX_CPU_TO_BUS_ADDR;

	pp->cfg0_mod_base &= DRA7XX_CPU_TO_BUS_ADDR;

	pp->cfg1_mod_base &= DRA7XX_CPU_TO_BUS_ADDR;



	dra7xx_pcie_establish_link(pp);

	dra7xx_pcie_establish_link(pp);

	if (IS_ENABLED(CONFIG_PCI_MSI))

	if (IS_ENABLED(CONFIG_PCI_MSI))

		dw_pcie_msi_init(pp);

		dw_pcie_msi_init(pp);

drivers/pci/host/pcie-designware.c

+4 −11
Original line number Original line Diff line number Diff line
@@ -417,14 +417,10 @@ int dw_pcie_host_init(struct pcie_port *pp) 
	struct of_pci_range range;

	struct of_pci_range range;

	struct of_pci_range_parser parser;

	struct of_pci_range_parser parser;

	struct resource *cfg_res;

	struct resource *cfg_res;

	u32 val, na, ns;

	u32 val, ns;

	const __be32 *addrp;

	const __be32 *addrp;

	int i, index, ret;

	int i, index, ret;





	/* Find the address cell size and the number of cells in order to get

	 * the untranslated address.

	 */

	of_property_read_u32(np, "#address-cells", &na);

	ns = of_n_size_cells(np);

	ns = of_n_size_cells(np);





	cfg_res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "config");

	cfg_res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "config");
@@ -467,8 +463,7 @@ int dw_pcie_host_init(struct pcie_port *pp) 
			pp->io_base = range.cpu_addr;

			pp->io_base = range.cpu_addr;





			/* Find the untranslated IO space address */

			/* Find the untranslated IO space address */

			pp->io_mod_base = of_read_number(parser.range -

			pp->io_mod_base = range.cpu_addr;

							 parser.np + na, ns);

		}

		}

		if (restype == IORESOURCE_MEM) {

		if (restype == IORESOURCE_MEM) {

			of_pci_range_to_resource(&range, np, &pp->mem);

			of_pci_range_to_resource(&range, np, &pp->mem);
@@ -477,8 +472,7 @@ int dw_pcie_host_init(struct pcie_port *pp) 
			pp->mem_bus_addr = range.pci_addr;

			pp->mem_bus_addr = range.pci_addr;





			/* Find the untranslated MEM space address */

			/* Find the untranslated MEM space address */

			pp->mem_mod_base = of_read_number(parser.range -

			pp->mem_mod_base = range.cpu_addr;

							  parser.np + na, ns);

		}

		}

		if (restype == 0) {

		if (restype == 0) {

			of_pci_range_to_resource(&range, np, &pp->cfg);

			of_pci_range_to_resource(&range, np, &pp->cfg);
@@ -488,8 +482,7 @@ int dw_pcie_host_init(struct pcie_port *pp) 
			pp->cfg1_base = pp->cfg.start + pp->cfg0_size;

			pp->cfg1_base = pp->cfg.start + pp->cfg0_size;





			/* Find the untranslated configuration space address */

			/* Find the untranslated configuration space address */

			pp->cfg0_mod_base = of_read_number(parser.range -

			pp->cfg0_mod_base = range.cpu_addr;

							   parser.np + na, ns);

			pp->cfg1_mod_base = pp->cfg0_mod_base +

			pp->cfg1_mod_base = pp->cfg0_mod_base +

					    pp->cfg0_size;

					    pp->cfg0_size;

		}

		}