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Commit 85aaeece authored by qctecmdr's avatar qctecmdr Committed by Gerrit - the friendly Code Review server
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Merge "ARM: dts: msm: Add LMH-DCVSh configuration for LITO"

parents 0ce29962 931bd919

bindings/thermal/qcom-lmh-dcvs.txt

+6 −0
Original line number Diff line number Diff line
@@ -57,6 +57,12 @@ Properties: 
			register space in index 0 should be LLM and index 1

			should be OSM.



- qcom,no-cooling-device-register:

	Usage: optional

	Value type: <none>

	Definition: Should define this property if this driver doesn't need

			to register CPU cooling devices with thermal framework.



Example:



	lmh_dcvs0: qcom,limits-dcvs@18350800 {

qcom/lito-thermal.dtsi

+32 −0
Original line number Diff line number Diff line 
#include <dt-bindings/thermal/thermal.h>



&cpufreq_hw {

	#address-cells = <1>;

	#size-cells = <1>;

	qcom,cpu-isolation {

		compatible = "qcom,cpu-isolate";

		cpu0_isolate: cpu0-isolate {
@@ -43,6 +45,36 @@ 
			#cooling-cells = <2>;

		};

	};



	lmh_dcvs0: qcom,limits-dcvs@18358800 {

		compatible = "qcom,msm-hw-limits";

		interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;

		qcom,affinity = <0>;

		reg = <0x18358800 0x1000>,

			<0x18323000 0x1000>;

		qcom,no-cooling-device-register;

		#thermal-sensor-cells = <0>;

	};



	lmh_dcvs1: qcom,limits-dcvs@18350800 {

		compatible = "qcom,msm-hw-limits";

		interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>;

		qcom,affinity = <1>;

		reg = <0x18350800 0x1000>,

			<0x18325800 0x1000>;

		qcom,no-cooling-device-register;

		#thermal-sensor-cells = <0>;

	};



	lmh_dcvs2: qcom,limits-dcvs@18327800 {

		compatible = "qcom,msm-hw-limits";

		interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>;

		qcom,affinity = <1>;

		reg = <0x18350800 0x1000>,

			<0x18327800 0x1000>;

		qcom,no-cooling-device-register;

		#thermal-sensor-cells = <0>;

	};

};



&soc {

qcom/lito.dtsi

+8 −0
Original line number Diff line number Diff line
@@ -59,6 +59,7 @@ 
			cache-size = <0x8000>;

			qcom,freq-domain = <&cpufreq_hw 0 6>;

			next-level-cache = <&L2_0>;

			qcom,lmh-dcvs = <&lmh_dcvs0>;

			#cooling-cells = <2>;

			L2_0: l2-cache {

			      compatible = "arm,arch-cache";
@@ -98,6 +99,7 @@ 
			cache-size = <0x8000>;

			qcom,freq-domain = <&cpufreq_hw 0 6>;

			next-level-cache = <&L2_100>;

			qcom,lmh-dcvs = <&lmh_dcvs0>;

			L2_100: l2-cache {

				compatible = "arm,arch-cache";

				cache-size = <0x10000>;
@@ -130,6 +132,7 @@ 
			cache-size = <0x8000>;

			qcom,freq-domain = <&cpufreq_hw 0 6>;

			next-level-cache = <&L2_200>;

			qcom,lmh-dcvs = <&lmh_dcvs0>;

			L2_200: l2-cache {

				compatible = "arm,arch-cache";

				cache-size = <0x10000>;
@@ -162,6 +165,7 @@ 
			cache-size = <0x8000>;

			qcom,freq-domain = <&cpufreq_hw 0 6>;

			next-level-cache = <&L2_300>;

			qcom,lmh-dcvs = <&lmh_dcvs0>;

			L2_300: l2-cache {

				compatible = "arm,arch-cache";

				cache-size = <0x10000>;
@@ -195,6 +199,7 @@ 
			cache-size = <0x8000>;

			qcom,freq-domain = <&cpufreq_hw 0 6>;

			next-level-cache = <&L2_400>;

			qcom,lmh-dcvs = <&lmh_dcvs0>;

			L2_400: l2-cache {

				compatible = "arm,arch-cache";

				cache-size = <0x10000>;
@@ -227,6 +232,7 @@ 
			cache-size = <0x8000>;

			qcom,freq-domain = <&cpufreq_hw 0 6>;

			next-level-cache = <&L2_500>;

			qcom,lmh-dcvs = <&lmh_dcvs0>;

			L2_500: l2-cache {

				compatible = "arm,arch-cache";

				cache-size = <0x10000>;
@@ -259,6 +265,7 @@ 
			cache-size = <0x10000>;

			qcom,freq-domain = <&cpufreq_hw 1 2>;

			next-level-cache = <&L2_600>;

			qcom,lmh-dcvs = <&lmh_dcvs1>;

			#cooling-cells = <2>;

			L2_600: l2-cache {

				compatible = "arm,arch-cache";
@@ -301,6 +308,7 @@ 
			cache-size = <0x10000>;

			qcom,freq-domain = <&cpufreq_hw 2 2>;

			next-level-cache = <&L2_700>;

			qcom,lmh-dcvs = <&lmh_dcvs2>;

			#cooling-cells = <2>;

			L2_700: l2-cache {

				compatible = "arm,arch-cache";