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Commit 931bd919 authored by Manaf Meethalavalappu Pallikunhi's avatar Manaf Meethalavalappu Pallikunhi
Browse files

ARM: dts: msm: Add LMH-DCVSh configuration for LITO 

Add LMH-DCVSh device configuration like debug interrupt and cluster
affinity value for LITO. Add the CPU to LMH-DCVSh hardware mapping,
monitor LMH DCVSh interrupts and notify throttling information to
scheduler, along with the LMH thermal zone definition.

Change-Id: I64c35fba4ec6794c3cf234974e3e9a33a6f2eac9
parent 9c2693ec

qcom/lito-thermal.dtsi

+32 −0
Original line number Original line Diff line number Diff line 
#include <dt-bindings/thermal/thermal.h>

#include <dt-bindings/thermal/thermal.h>





&cpufreq_hw {

&cpufreq_hw {

	#address-cells = <1>;

	#size-cells = <1>;

	qcom,cpu-isolation {

	qcom,cpu-isolation {

		compatible = "qcom,cpu-isolate";

		compatible = "qcom,cpu-isolate";

		cpu0_isolate: cpu0-isolate {

		cpu0_isolate: cpu0-isolate {
@@ -43,6 +45,36 @@ 
			#cooling-cells = <2>;

			#cooling-cells = <2>;

		};

		};

	};

	};



	lmh_dcvs0: qcom,limits-dcvs@18358800 {

		compatible = "qcom,msm-hw-limits";

		interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;

		qcom,affinity = <0>;

		reg = <0x18358800 0x1000>,

			<0x18323000 0x1000>;

		qcom,no-cooling-device-register;

		#thermal-sensor-cells = <0>;

	};



	lmh_dcvs1: qcom,limits-dcvs@18350800 {

		compatible = "qcom,msm-hw-limits";

		interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>;

		qcom,affinity = <1>;

		reg = <0x18350800 0x1000>,

			<0x18325800 0x1000>;

		qcom,no-cooling-device-register;

		#thermal-sensor-cells = <0>;

	};



	lmh_dcvs2: qcom,limits-dcvs@18327800 {

		compatible = "qcom,msm-hw-limits";

		interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>;

		qcom,affinity = <1>;

		reg = <0x18350800 0x1000>,

			<0x18327800 0x1000>;

		qcom,no-cooling-device-register;

		#thermal-sensor-cells = <0>;

	};

};

};





&soc {

&soc {

qcom/lito.dtsi

+8 −0
Original line number Original line Diff line number Diff line
@@ -50,6 +50,7 @@ 
			cache-size = <0x8000>;

			cache-size = <0x8000>;

			qcom,freq-domain = <&cpufreq_hw 0 6>;

			qcom,freq-domain = <&cpufreq_hw 0 6>;

			next-level-cache = <&L2_0>;

			next-level-cache = <&L2_0>;

			qcom,lmh-dcvs = <&lmh_dcvs0>;

			#cooling-cells = <2>;

			#cooling-cells = <2>;

			L2_0: l2-cache {

			L2_0: l2-cache {

			      compatible = "arm,arch-cache";

			      compatible = "arm,arch-cache";
@@ -89,6 +90,7 @@ 
			cache-size = <0x8000>;

			cache-size = <0x8000>;

			qcom,freq-domain = <&cpufreq_hw 0 6>;

			qcom,freq-domain = <&cpufreq_hw 0 6>;

			next-level-cache = <&L2_100>;

			next-level-cache = <&L2_100>;

			qcom,lmh-dcvs = <&lmh_dcvs0>;

			L2_100: l2-cache {

			L2_100: l2-cache {

				compatible = "arm,arch-cache";

				compatible = "arm,arch-cache";

				cache-size = <0x10000>;

				cache-size = <0x10000>;
@@ -121,6 +123,7 @@ 
			cache-size = <0x8000>;

			cache-size = <0x8000>;

			qcom,freq-domain = <&cpufreq_hw 0 6>;

			qcom,freq-domain = <&cpufreq_hw 0 6>;

			next-level-cache = <&L2_200>;

			next-level-cache = <&L2_200>;

			qcom,lmh-dcvs = <&lmh_dcvs0>;

			L2_200: l2-cache {

			L2_200: l2-cache {

				compatible = "arm,arch-cache";

				compatible = "arm,arch-cache";

				cache-size = <0x10000>;

				cache-size = <0x10000>;
@@ -153,6 +156,7 @@ 
			cache-size = <0x8000>;

			cache-size = <0x8000>;

			qcom,freq-domain = <&cpufreq_hw 0 6>;

			qcom,freq-domain = <&cpufreq_hw 0 6>;

			next-level-cache = <&L2_300>;

			next-level-cache = <&L2_300>;

			qcom,lmh-dcvs = <&lmh_dcvs0>;

			L2_300: l2-cache {

			L2_300: l2-cache {

				compatible = "arm,arch-cache";

				compatible = "arm,arch-cache";

				cache-size = <0x10000>;

				cache-size = <0x10000>;
@@ -186,6 +190,7 @@ 
			cache-size = <0x8000>;

			cache-size = <0x8000>;

			qcom,freq-domain = <&cpufreq_hw 0 6>;

			qcom,freq-domain = <&cpufreq_hw 0 6>;

			next-level-cache = <&L2_400>;

			next-level-cache = <&L2_400>;

			qcom,lmh-dcvs = <&lmh_dcvs0>;

			L2_400: l2-cache {

			L2_400: l2-cache {

				compatible = "arm,arch-cache";

				compatible = "arm,arch-cache";

				cache-size = <0x10000>;

				cache-size = <0x10000>;
@@ -218,6 +223,7 @@ 
			cache-size = <0x8000>;

			cache-size = <0x8000>;

			qcom,freq-domain = <&cpufreq_hw 0 6>;

			qcom,freq-domain = <&cpufreq_hw 0 6>;

			next-level-cache = <&L2_500>;

			next-level-cache = <&L2_500>;

			qcom,lmh-dcvs = <&lmh_dcvs0>;

			L2_500: l2-cache {

			L2_500: l2-cache {

				compatible = "arm,arch-cache";

				compatible = "arm,arch-cache";

				cache-size = <0x10000>;

				cache-size = <0x10000>;
@@ -250,6 +256,7 @@ 
			cache-size = <0x10000>;

			cache-size = <0x10000>;

			qcom,freq-domain = <&cpufreq_hw 1 2>;

			qcom,freq-domain = <&cpufreq_hw 1 2>;

			next-level-cache = <&L2_600>;

			next-level-cache = <&L2_600>;

			qcom,lmh-dcvs = <&lmh_dcvs1>;

			#cooling-cells = <2>;

			#cooling-cells = <2>;

			L2_600: l2-cache {

			L2_600: l2-cache {

				compatible = "arm,arch-cache";

				compatible = "arm,arch-cache";
@@ -292,6 +299,7 @@ 
			cache-size = <0x10000>;

			cache-size = <0x10000>;

			qcom,freq-domain = <&cpufreq_hw 2 2>;

			qcom,freq-domain = <&cpufreq_hw 2 2>;

			next-level-cache = <&L2_700>;

			next-level-cache = <&L2_700>;

			qcom,lmh-dcvs = <&lmh_dcvs2>;

			#cooling-cells = <2>;

			#cooling-cells = <2>;

			L2_700: l2-cache {

			L2_700: l2-cache {

				compatible = "arm,arch-cache";

				compatible = "arm,arch-cache";