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Commit 84e0f1c1 authored by Igal Liberman's avatar Igal Liberman Committed by Scott Wood
Browse files

powerpc/mpc85xx: Add MDIO bus muxing support to the board device tree(s) 



Describe the PHY topology for all configurations supported by each board

Based on prior work by Andy Fleming <afleming@freescale.com>

Signed-off-by: default avatarShruti Kanetkar <Shruti@freescale.com>
Signed-off-by: default avatarEmil Medve <Emilian.Medve@Freescale.com>
Signed-off-by: default avatarIgal Liberman <Igal.Liberman@freescale.com>
Signed-off-by: default avatarScott Wood <oss@buserror.net>
parent 334479d1

arch/powerpc/boot/dts/fsl/b4860qds.dts

+58 −2
Original line number Diff line number Diff line 
/*

 * B4860DS Device Tree Source

 *

 * Copyright 2012 Freescale Semiconductor Inc.

 * Copyright 2012 - 2015 Freescale Semiconductor Inc.

 *

 * Redistribution and use in source and binary forms, with or without

 * modification, are permitted provided that the following conditions are met:
@@ -39,12 +39,69 @@ 
	model = "fsl,B4860QDS";

	compatible = "fsl,B4860QDS";



	aliases {

		phy_sgmii_1e = &phy_sgmii_1e;

		phy_sgmii_1f = &phy_sgmii_1f;

		phy_xaui_slot1 = &phy_xaui_slot1;

		phy_xaui_slot2 = &phy_xaui_slot2;

	};



	ifc: localbus@ffe124000 {

		board-control@3,0 {

			compatible = "fsl,b4860qds-fpga", "fsl,fpga-qixis";

		};

	};



	soc@ffe000000 {

		fman@400000 {

			ethernet@e8000 {

				phy-handle = <&phy_sgmii_1e>;

				phy-connection-type = "sgmii";

			};



			ethernet@ea000 {

				phy-handle = <&phy_sgmii_1f>;

				phy-connection-type = "sgmii";

			};



			ethernet@f0000 {

				phy-handle = <&phy_xaui_slot1>;

				phy-connection-type = "xgmii";

			};



			ethernet@f2000 {

				phy-handle = <&phy_xaui_slot2>;

				phy-connection-type = "xgmii";

			};



			mdio@fc000 {

				phy_sgmii_1e: ethernet-phy@1e {

					reg = <0x1e>;

					status = "disabled";

				};



				phy_sgmii_1f: ethernet-phy@1f {

					reg = <0x1f>;

					status = "disabled";

				};

			};



			mdio@fd000 {

				phy_xaui_slot1: xaui-phy@slot1 {

					compatible = "ethernet-phy-ieee802.3-c45";

					reg = <0x7>;

					status = "disabled";

				};



				phy_xaui_slot2: xaui-phy@slot2 {

					compatible = "ethernet-phy-ieee802.3-c45";

					reg = <0x6>;

					status = "disabled";

				};

			};

		};

	};



	rio: rapidio@ffe0c0000 {

		reg = <0xf 0xfe0c0000 0 0x11000>;
@@ -55,7 +112,6 @@ 
			ranges = <0 0 0xc 0x30000000 0 0x10000000>;

		};

	};



};



/include/ "b4860si-post.dtsi"

arch/powerpc/boot/dts/fsl/b4qds.dtsi

+49 −2
Original line number Diff line number Diff line 
/*

 * B4420DS Device Tree Source

 *

 * Copyright 2012 - 2014 Freescale Semiconductor, Inc.

 * Copyright 2012 - 2015 Freescale Semiconductor, Inc.

 *

 * Redistribution and use in source and binary forms, with or without

 * modification, are permitted provided that the following conditions are met:
@@ -39,6 +39,13 @@ 
	#size-cells = <2>;

	interrupt-parent = <&mpic>;



	aliases {

		phy_sgmii_10 = &phy_sgmii_10;

		phy_sgmii_11 = &phy_sgmii_11;

		phy_sgmii_1c = &phy_sgmii_1c;

		phy_sgmii_1d = &phy_sgmii_1d;

	};



	ifc: localbus@ffe124000 {

		reg = <0xf 0xfe124000 0 0x2000>;

		ranges = <0 0 0xf 0xe8000000 0x08000000
@@ -210,6 +217,47 @@ 
			phy_type = "ulpi";

		};



		fman@400000 {

			ethernet@e0000 {

				phy-handle = <&phy_sgmii_10>;

				phy-connection-type = "sgmii";

			};



			ethernet@e2000 {

				phy-handle = <&phy_sgmii_11>;

				phy-connection-type = "sgmii";

			};



			ethernet@e4000 {

				phy-handle = <&phy_sgmii_1c>;

				phy-connection-type = "sgmii";

			};



			ethernet@e6000 {

				phy-handle = <&phy_sgmii_1d>;

				phy-connection-type = "sgmii";

			};



			mdio@fc000 {

				phy_sgmii_10: ethernet-phy@10 {

					reg = <0x10>;

				};



				phy_sgmii_11: ethernet-phy@11 {

					reg = <0x11>;

				};



				phy_sgmii_1c: ethernet-phy@1c {

					reg = <0x1c>;

					status = "disabled";

				};



				phy_sgmii_1d: ethernet-phy@1d {

					reg = <0x1d>;

					status = "disabled";

				};

			};

		};

	};



	pci0: pcie@ffe200000 {
@@ -226,7 +274,6 @@ 
				  0 0x00010000>;

		};

	};



};



/include/ "b4si-post.dtsi"

arch/powerpc/boot/dts/fsl/p2041rdb.dts

+91 −1
Original line number Diff line number Diff line 
/*

 * P2041RDB Device Tree Source

 *

 * Copyright 2011 - 2014 Freescale Semiconductor Inc.

 * Copyright 2011 - 2015 Freescale Semiconductor Inc.

 *

 * Redistribution and use in source and binary forms, with or without

 * modification, are permitted provided that the following conditions are met:
@@ -41,6 +41,19 @@ 
	#size-cells = <2>;

	interrupt-parent = <&mpic>;



	aliases {

		phy_rgmii_0 = &phy_rgmii_0;

		phy_rgmii_1 = &phy_rgmii_1;

		phy_sgmii_2 = &phy_sgmii_2;

		phy_sgmii_3 = &phy_sgmii_3;

		phy_sgmii_4 = &phy_sgmii_4;

		phy_sgmii_1c = &phy_sgmii_1c;

		phy_sgmii_1d = &phy_sgmii_1d;

		phy_sgmii_1e = &phy_sgmii_1e;

		phy_sgmii_1f = &phy_sgmii_1f;

		phy_xgmii_2 = &phy_xgmii_2;

	};



	memory {

		device_type = "memory";

	};
@@ -137,6 +150,83 @@ 
		usb1: usb@211000 {

			dr_mode = "host";

		};



		fman@400000 {

			ethernet@e0000 {

				phy-handle = <&phy_sgmii_2>;

				phy-connection-type = "sgmii";

			};



			mdio@e1120 {

				phy_rgmii_0: ethernet-phy@0 {

					reg = <0x0>;

				};



				phy_rgmii_1: ethernet-phy@1 {

					reg = <0x1>;

				};



				phy_sgmii_2: ethernet-phy@2 {

					reg = <0x2>;

				};



				phy_sgmii_3: ethernet-phy@3 {

					reg = <0x3>;

				};



				phy_sgmii_4: ethernet-phy@4 {

					reg = <0x4>;

				};



				phy_sgmii_1c: ethernet-phy@1c {

					reg = <0x1c>;

				};



				phy_sgmii_1d: ethernet-phy@1d {

					reg = <0x1d>;

				};



				phy_sgmii_1e: ethernet-phy@1e {

					reg = <0x1e>;

				};



				phy_sgmii_1f: ethernet-phy@1f {

					reg = <0x1f>;

				};

			};



			ethernet@e2000 {

				phy-handle = <&phy_sgmii_3>;

				phy-connection-type = "sgmii";

			};



			ethernet@e4000 {

				phy-handle = <&phy_sgmii_4>;

				phy-connection-type = "sgmii";

			};



			ethernet@e6000 {

				phy-handle = <&phy_rgmii_1>;

				phy-connection-type = "rgmii";

			};



			ethernet@e8000 {

				phy-handle = <&phy_rgmii_0>;

				phy-connection-type = "rgmii";

			};



			ethernet@f0000 {

				phy-handle = <&phy_xgmii_2>;

				phy-connection-type = "xgmii";

			};



			mdio@f1000 {

				phy_xgmii_2: ethernet-phy@0 {

					compatible = "ethernet-phy-ieee802.3-c45";

					reg = <0x0>;

				};

			};

		};

	};



	rio: rapidio@ffe0c0000 {

arch/powerpc/boot/dts/fsl/p3041ds.dts

+111 −1
Original line number Diff line number Diff line 
/*

 * P3041DS Device Tree Source

 *

 * Copyright 2010 - 2014 Freescale Semiconductor Inc.

 * Copyright 2010 - 2015 Freescale Semiconductor Inc.

 *

 * Redistribution and use in source and binary forms, with or without

 * modification, are permitted provided that the following conditions are met:
@@ -41,6 +41,20 @@ 
	#size-cells = <2>;

	interrupt-parent = <&mpic>;



	aliases{

		phy_rgmii_0 = &phy_rgmii_0;

		phy_rgmii_1 = &phy_rgmii_1;

		phy_sgmii_1c = &phy_sgmii_1c;

		phy_sgmii_1d = &phy_sgmii_1d;

		phy_sgmii_1e = &phy_sgmii_1e;

		phy_sgmii_1f = &phy_sgmii_1f;

		phy_xgmii_1 = &phy_xgmii_1;

		phy_xgmii_2 = &phy_xgmii_2;

		emi1_rgmii = &hydra_mdio_rgmii;

		emi1_sgmii = &hydra_mdio_sgmii;

		emi2_xgmii = &hydra_mdio_xgmii;

	};



	memory {

		device_type = "memory";

	};
@@ -150,6 +164,52 @@ 
				reg = <0x4c>;

			};

		};



		fman@400000{

			ethernet@e0000 {

				phy-handle = <&phy_sgmii_1c>;

				phy-connection-type = "sgmii";

			};



			ethernet@e2000 {

				phy-handle = <&phy_sgmii_1d>;

				phy-connection-type = "sgmii";

			};



			ethernet@e4000 {

				phy-handle = <&phy_sgmii_1e>;

				phy-connection-type = "sgmii";

			};



			ethernet@e6000 {

				phy-handle = <&phy_sgmii_1f>;

				phy-connection-type = "sgmii";

			};



			ethernet@e8000 {

				phy-handle = <&phy_rgmii_1>;

				phy-connection-type = "rgmii";

			};



			ethernet@f0000 {

				phy-handle = <&phy_xgmii_1>;

				phy-connection-type = "xgmii";

			};



			hydra_mdio_xgmii: mdio@f1000 {

				status = "disabled";



				phy_xgmii_1: ethernet-phy@4 {

					compatible = "ethernet-phy-ieee802.3-c45";

					reg = <0x4>;

				};



				phy_xgmii_2: ethernet-phy@0 {

					compatible = "ethernet-phy-ieee802.3-c45";

					reg = <0x0>;

				};

			};

		};

	};



	rio: rapidio@ffe0c0000 {
@@ -215,8 +275,58 @@ 
		};



		board-control@3,0 {

			#address-cells = <1>;

			#size-cells = <1>;

			compatible = "fsl,p3041ds-fpga", "fsl,fpga-ngpixis";

			reg = <3 0 0x30>;

			ranges = <0 3 0 0x30>;



			mdio-mux-emi1 {

				#address-cells = <1>;

				#size-cells = <0>;

				compatible = "mdio-mux-mmioreg", "mdio-mux";

				mdio-parent-bus = <&mdio0>;

				reg = <9 1>;

				mux-mask = <0x78>;



				hydra_mdio_rgmii: rgmii-mdio@8 {

					#address-cells = <1>;

					#size-cells = <0>;

					reg = <8>;

					status = "disabled";



					phy_rgmii_0: ethernet-phy@0 {

						reg = <0x0>;

					};



					phy_rgmii_1: ethernet-phy@1 {

						reg = <0x1>;

					};

				};



				hydra_mdio_sgmii: sgmii-mdio@28 {

					#address-cells = <1>;

					#size-cells = <0>;

					reg = <0x28>;

					status = "disabled";



					phy_sgmii_1c: ethernet-phy@1c {

						reg = <0x1c>;

					};



					phy_sgmii_1d: ethernet-phy@1d {

						reg = <0x1d>;

					};



					phy_sgmii_1e: ethernet-phy@1e {

						reg = <0x1e>;

					};



					phy_sgmii_1f: ethernet-phy@1f {

						reg = <0x1f>;

					};

				};

			};

		};

	};

arch/powerpc/boot/dts/fsl/p4080ds.dts

+183 −1
Original line number Diff line number Diff line 
/*

 * P4080DS Device Tree Source

 *

 * Copyright 2009 - 2014 Freescale Semiconductor Inc.

 * Copyright 2009 - 2015 Freescale Semiconductor Inc.

 *

 * Redistribution and use in source and binary forms, with or without

 * modification, are permitted provided that the following conditions are met:
@@ -41,6 +41,20 @@ 
	#size-cells = <2>;

	interrupt-parent = <&mpic>;



	aliases {

		phy_rgmii = &phyrgmii;

		phy5_slot3 = &phy5slot3;

		phy6_slot3 = &phy6slot3;

		phy7_slot3 = &phy7slot3;

		phy8_slot3 = &phy8slot3;

		emi1_slot3 = &p4080mdio2;

		emi1_slot4 = &p4080mdio1;

		emi1_slot5 = &p4080mdio3;

		emi1_rgmii = &p4080mdio0;

		emi2_slot4 = &p4080xmdio1;

		emi2_slot5 = &p4080xmdio3;

	};



	memory {

		device_type = "memory";

	};
@@ -137,6 +151,60 @@ 
			dr_mode = "host";

			phy_type = "ulpi";

		};



		fman@400000 {

			ethernet@e0000 {

				phy-handle = <&phy0>;

				phy-connection-type = "sgmii";

			};



			ethernet@e2000 {

				phy-handle = <&phy1>;

				phy-connection-type = "sgmii";

			};



			ethernet@e4000 {

				phy-handle = <&phy2>;

				phy-connection-type = "sgmii";

			};



			ethernet@e6000 {

				phy-handle = <&phy3>;

				phy-connection-type = "sgmii";

			};



			ethernet@f0000 {

				phy-handle = <&phy10>;

				phy-connection-type = "xgmii";

			};

		};



		fman@500000 {

			ethernet@e0000 {

				phy-handle = <&phy5>;

				phy-connection-type = "sgmii";

			};



			ethernet@e2000 {

				phy-handle = <&phy6>;

				phy-connection-type = "sgmii";

			};



			ethernet@e4000 {

				phy-handle = <&phy7>;

				phy-connection-type = "sgmii";

			};



			ethernet@e6000 {

				phy-handle = <&phy8>;

				phy-connection-type = "sgmii";

			};



			ethernet@f0000 {

				phy-handle = <&phy11>;

				phy-connection-type = "xgmii";

			};

		};

	};



	rio: rapidio@ffe0c0000 {
@@ -213,6 +281,120 @@ 
		};

	};



	mdio-mux-emi1 {

		#address-cells = <1>;

		#size-cells = <0>;

		compatible = "mdio-mux-gpio", "mdio-mux";

		mdio-parent-bus = <&mdio0>;

		gpios = <&gpio0 1 0>, <&gpio0 0 0>;



		p4080mdio0: mdio@0 {

			#address-cells = <1>;

			#size-cells = <0>;

			reg = <0>;



			phyrgmii: ethernet-phy@0 {

				reg = <0x0>;

			};

		};



		p4080mdio1: mdio@1 {

			#address-cells = <1>;

			#size-cells = <0>;

			reg = <1>;



			phy5: ethernet-phy@1c {

				reg = <0x1c>;

			};



			phy6: ethernet-phy@1d {

				reg = <0x1d>;

			};



			phy7: ethernet-phy@1e {

				reg = <0x1e>;

			};



			phy8: ethernet-phy@1f {

				reg = <0x1f>;

			};

		};



		p4080mdio2: mdio@2 {

			#address-cells = <1>;

			#size-cells = <0>;

			reg = <2>;

			status = "disabled";



			phy5slot3: ethernet-phy@1c {

				reg = <0x1c>;

			};



			phy6slot3: ethernet-phy@1d {

				reg = <0x1d>;

			};



			phy7slot3: ethernet-phy@1e {

				reg = <0x1e>;

			};



			phy8slot3: ethernet-phy@1f {

				reg = <0x1f>;

			};

		};



		p4080mdio3: mdio@3 {

			#address-cells = <1>;

			#size-cells = <0>;

			reg = <3>;



			phy0: ethernet-phy@1c {

				reg = <0x1c>;

			};



			phy1: ethernet-phy@1d {

				reg = <0x1d>;

			};



			phy2: ethernet-phy@1e {

				reg = <0x1e>;

			};



			phy3: ethernet-phy@1f {

				reg = <0x1f>;

			};

		};

	};



	mdio-mux-emi2 {

		#address-cells = <1>;

		#size-cells = <0>;

		compatible = "mdio-mux-gpio", "mdio-mux";

		mdio-parent-bus = <&xmdio0>;

		gpios = <&gpio0 3 0>, <&gpio0 2 0>;



		p4080xmdio1: mdio@1 {

			#address-cells = <1>;

			#size-cells = <0>;

			reg = <1>;



			phy11: ethernet-phy@0 {

				compatible = "ethernet-phy-ieee802.3-c45";

				reg = <0x0>;

			};

		};



		p4080xmdio3: mdio@3 {

			#address-cells = <1>;

			#size-cells = <0>;

			reg = <3>;



			phy10: ethernet-phy@4 {

				compatible = "ethernet-phy-ieee802.3-c45";

				reg = <0x4>;

			};

		};

	};

};



/include/ "p4080si-post.dtsi"