Loading drivers/clk/qcom/debugcc-scuba.c +0 −2 Original line number Diff line number Diff line Loading @@ -156,7 +156,6 @@ static const char *const gcc_debug_mux_parent_names[] = { "gcc_gpu_memnoc_gfx_clk", "gcc_gpu_snoc_dvm_gfx_clk", "gcc_gpu_throttle_core_clk", "gcc_gpu_throttle_xo_clk", "gcc_mss_vs_clk", "gcc_pdm2_clk", "gcc_pdm_ahb_clk", Loading Loading @@ -267,7 +266,6 @@ static int gcc_debug_mux_sels[] = { 0xE4, /* gcc_gpu_memnoc_gfx_clk */ 0xE6, /* gcc_gpu_snoc_dvm_gfx_clk */ 0xEB, /* gcc_gpu_throttle_core_clk */ 0xEA, /* gcc_gpu_throttle_xo_clk */ 0xBE, /* gcc_mss_vs_clk */ 0x72, /* gcc_pdm2_clk */ 0x70, /* gcc_pdm_ahb_clk */ Loading drivers/clk/qcom/gcc-scuba.c +0 −14 Original line number Diff line number Diff line Loading @@ -2465,19 +2465,6 @@ static struct clk_branch gcc_gpu_throttle_core_clk = { }, }; static struct clk_branch gcc_gpu_throttle_xo_clk = { .halt_reg = 0x36044, .halt_check = BRANCH_HALT, .clkr = { .enable_reg = 0x36044, .enable_mask = BIT(0), .hw.init = &(struct clk_init_data){ .name = "gcc_gpu_throttle_xo_clk", .ops = &clk_branch2_ops, }, }, }; static struct clk_branch gcc_pdm2_clk = { .halt_reg = 0x2000c, .halt_check = BRANCH_HALT, Loading Loading @@ -3192,7 +3179,6 @@ static struct clk_regmap *gcc_scuba_clocks[] = { [GCC_GPU_MEMNOC_GFX_CLK] = &gcc_gpu_memnoc_gfx_clk.clkr, [GCC_GPU_SNOC_DVM_GFX_CLK] = &gcc_gpu_snoc_dvm_gfx_clk.clkr, [GCC_GPU_THROTTLE_CORE_CLK] = &gcc_gpu_throttle_core_clk.clkr, [GCC_GPU_THROTTLE_XO_CLK] = &gcc_gpu_throttle_xo_clk.clkr, [GCC_PDM2_CLK] = &gcc_pdm2_clk.clkr, [GCC_PDM2_CLK_SRC] = &gcc_pdm2_clk_src.clkr, [GCC_PDM_AHB_CLK] = &gcc_pdm_ahb_clk.clkr, Loading Loading
drivers/clk/qcom/debugcc-scuba.c +0 −2 Original line number Diff line number Diff line Loading @@ -156,7 +156,6 @@ static const char *const gcc_debug_mux_parent_names[] = { "gcc_gpu_memnoc_gfx_clk", "gcc_gpu_snoc_dvm_gfx_clk", "gcc_gpu_throttle_core_clk", "gcc_gpu_throttle_xo_clk", "gcc_mss_vs_clk", "gcc_pdm2_clk", "gcc_pdm_ahb_clk", Loading Loading @@ -267,7 +266,6 @@ static int gcc_debug_mux_sels[] = { 0xE4, /* gcc_gpu_memnoc_gfx_clk */ 0xE6, /* gcc_gpu_snoc_dvm_gfx_clk */ 0xEB, /* gcc_gpu_throttle_core_clk */ 0xEA, /* gcc_gpu_throttle_xo_clk */ 0xBE, /* gcc_mss_vs_clk */ 0x72, /* gcc_pdm2_clk */ 0x70, /* gcc_pdm_ahb_clk */ Loading
drivers/clk/qcom/gcc-scuba.c +0 −14 Original line number Diff line number Diff line Loading @@ -2465,19 +2465,6 @@ static struct clk_branch gcc_gpu_throttle_core_clk = { }, }; static struct clk_branch gcc_gpu_throttle_xo_clk = { .halt_reg = 0x36044, .halt_check = BRANCH_HALT, .clkr = { .enable_reg = 0x36044, .enable_mask = BIT(0), .hw.init = &(struct clk_init_data){ .name = "gcc_gpu_throttle_xo_clk", .ops = &clk_branch2_ops, }, }, }; static struct clk_branch gcc_pdm2_clk = { .halt_reg = 0x2000c, .halt_check = BRANCH_HALT, Loading Loading @@ -3192,7 +3179,6 @@ static struct clk_regmap *gcc_scuba_clocks[] = { [GCC_GPU_MEMNOC_GFX_CLK] = &gcc_gpu_memnoc_gfx_clk.clkr, [GCC_GPU_SNOC_DVM_GFX_CLK] = &gcc_gpu_snoc_dvm_gfx_clk.clkr, [GCC_GPU_THROTTLE_CORE_CLK] = &gcc_gpu_throttle_core_clk.clkr, [GCC_GPU_THROTTLE_XO_CLK] = &gcc_gpu_throttle_xo_clk.clkr, [GCC_PDM2_CLK] = &gcc_pdm2_clk.clkr, [GCC_PDM2_CLK_SRC] = &gcc_pdm2_clk_src.clkr, [GCC_PDM_AHB_CLK] = &gcc_pdm_ahb_clk.clkr, Loading