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Commit 824f25c1 authored by Olof Johansson's avatar Olof Johansson
Browse files

Merge tag 'v4.1-rockchip-soc1' of... 

Merge tag 'v4.1-rockchip-soc1' of git://git.kernel.org/pub/scm/linux/kernel/git/mmind/linux-rockchip into next/soc

Merge "ARM: rockchip: soc code changes for 4.1" from Heiko Stuebner:

Some suspend improvements reducing resume time and making sure the
watchdog does not reset after 12 hours and a change to constify and
staticize some smp parts.

* tag 'v4.1-rockchip-soc1' of git://git.kernel.org/pub/scm/linux/kernel/git/mmind/linux-rockchip

:
  ARM: rockchip: disable watchdog during suspend
  ARM: rockchip: decrease the wait time for resume
  ARM: rockchip: Constify struct regmap_config and staticize local function

Signed-off-by: default avatarOlof Johansson <olof@lixom.net>
parents ffe971ef a0307d18

arch/arm/mach-rockchip/platsmp.c

+2 −2
Original line number Diff line number Diff line
@@ -55,7 +55,7 @@ static int pmu_power_domain_is_on(int pd) 
	return !(val & BIT(pd));

}



struct reset_control *rockchip_get_core_reset(int cpu)

static struct reset_control *rockchip_get_core_reset(int cpu)

{

	struct device *dev = get_cpu_device(cpu);

	struct device_node *np;
@@ -201,7 +201,7 @@ static int __init rockchip_smp_prepare_sram(struct device_node *node) 
	return 0;

}



static struct regmap_config rockchip_pmu_regmap_config = {

static const struct regmap_config rockchip_pmu_regmap_config = {

	.reg_bits = 32,

	.val_bits = 32,

	.reg_stride = 4,

arch/arm/mach-rockchip/pm.c

+11 −3
Original line number Diff line number Diff line
@@ -75,9 +75,13 @@ static void rk3288_slp_mode_set(int level) 
	regmap_read(pmu_regmap, RK3288_PMU_PWRMODE_CON,

		    &rk3288_pmu_pwr_mode_con);



	/* set bit 8 so that system will resume to FAST_BOOT_ADDR */

	/*

	 * SGRF_FAST_BOOT_EN - system to boot from FAST_BOOT_ADDR

	 * PCLK_WDT_GATE - disable WDT during suspend.

	 */

	regmap_write(sgrf_regmap, RK3288_SGRF_SOC_CON0,

		     SGRF_FAST_BOOT_EN | SGRF_FAST_BOOT_EN_WRITE);

		     SGRF_PCLK_WDT_GATE | SGRF_FAST_BOOT_EN

		     | SGRF_PCLK_WDT_GATE_WRITE | SGRF_FAST_BOOT_EN_WRITE);



	/* booting address of resuming system is from this register value */

	regmap_write(sgrf_regmap, RK3288_SGRF_FAST_BOOT_ADDR,
@@ -122,7 +126,8 @@ static void rk3288_slp_mode_set_resume(void) 
		     rk3288_pmu_pwr_mode_con);



	regmap_write(sgrf_regmap, RK3288_SGRF_SOC_CON0,

		     rk3288_sgrf_soc_con0 | SGRF_FAST_BOOT_EN_WRITE);

		     rk3288_sgrf_soc_con0 | SGRF_PCLK_WDT_GATE_WRITE

		     | SGRF_FAST_BOOT_EN_WRITE);

}



static int rockchip_lpmode_enter(unsigned long arg)
@@ -209,6 +214,9 @@ static int rk3288_suspend_init(struct device_node *np) 
	memcpy(rk3288_bootram_base, rockchip_slp_cpu_resume,

	       rk3288_bootram_sz);



	regmap_write(pmu_regmap, RK3288_PMU_OSC_CNT, OSC_STABL_CNT_THRESH);

	regmap_write(pmu_regmap, RK3288_PMU_STABL_CNT, PMU_STABL_CNT_THRESH);



	return 0;

}

arch/arm/mach-rockchip/pm.h

+6 −0
Original line number Diff line number Diff line
@@ -50,6 +50,8 @@ static inline void rockchip_suspend_init(void) 


#define RK3288_SGRF_SOC_CON0		(0x0000)

#define RK3288_SGRF_FAST_BOOT_ADDR	(0x0120)

#define SGRF_PCLK_WDT_GATE		BIT(6)

#define SGRF_PCLK_WDT_GATE_WRITE	BIT(22)

#define SGRF_FAST_BOOT_EN		BIT(8)

#define SGRF_FAST_BOOT_EN_WRITE		BIT(24)
@@ -63,6 +65,10 @@ static inline void rockchip_suspend_init(void) 
/* PMU_WAKEUP_CFG1 bits */

#define PMU_ARMINT_WAKEUP_EN		BIT(0)



/* wait 30ms for OSC stable and 30ms for pmic stable */

#define OSC_STABL_CNT_THRESH	(32 * 30)

#define PMU_STABL_CNT_THRESH	(32 * 30)



enum rk3288_pwr_mode_con {

	PMU_PWR_MODE_EN = 0,

	PMU_CLK_CORE_SRC_GATE_EN,