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Commit 81ef4479 authored by Gary Bisson's avatar Gary Bisson Committed by Shawn Guo
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ARM: clk-imx6q: fix video divider for rev T0 1.0 



The post dividers do not work on i.MX6Q rev T0 1.0 so they must be fixed
to 1. As the table index was wrong, a divider a of 4 could still be
requested which implied the clock not to be set properly. This is the
root cause of the HDMI not working at high resolution on rev T0 1.0 of
the SoC.

Signed-off-by: default avatarGary Bisson <bisson.gary@gmail.com>
Cc: <stable@vger.kernel.org>
Signed-off-by: default avatarShawn Guo <shawn.guo@linaro.org>
parent b2faf1a1

arch/arm/mach-imx/clk-imx6q.c

+1 −1
Original line number Diff line number Diff line
@@ -144,7 +144,7 @@ static void __init imx6q_clocks_init(struct device_node *ccm_node) 
		post_div_table[1].div = 1;

		post_div_table[2].div = 1;

		video_div_table[1].div = 1;

		video_div_table[2].div = 1;

		video_div_table[3].div = 1;

	}



	clk[IMX6QDL_PLL1_BYPASS_SRC] = imx_clk_mux("pll1_bypass_src", base + 0x00, 14, 2, pll_bypass_src_sels, ARRAY_SIZE(pll_bypass_src_sels));