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Commit b2faf1a1 authored by Philipp Zabel's avatar Philipp Zabel Committed by Shawn Guo
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ARM: dts: imx6qdl: Fix CODA960 interrupt order 



Commit a04a0b6f ("ARM: dts: imx6qdl: Enable CODA960 VPU") lost the
fix for the CODA960 interrupt order during a rebase before being applied.
This patch adds the missing bit and brings the interrupts and
interrupt-names properties back in sync.

Signed-off-by: default avatarPhilipp Zabel <p.zabel@pengutronix.de>
Reviewed-by: default avatarFabio Estevam <fabio.estevam@freescale.com>
Signed-off-by: default avatarShawn Guo <shawn.guo@linaro.org>
parent 4fe6be0f

arch/arm/boot/dts/imx6qdl.dtsi

+2 −2
Original line number Diff line number Diff line
@@ -335,8 +335,8 @@ 
			vpu: vpu@02040000 {

				compatible = "cnm,coda960";

				reg = <0x02040000 0x3c000>;

				interrupts = <0 3 IRQ_TYPE_LEVEL_HIGH>,

				             <0 12 IRQ_TYPE_LEVEL_HIGH>;

				interrupts = <0 12 IRQ_TYPE_LEVEL_HIGH>,

					     <0 3 IRQ_TYPE_LEVEL_HIGH>;

				interrupt-names = "bit", "jpeg";

				clocks = <&clks IMX6QDL_CLK_VPU_AXI>,

					 <&clks IMX6QDL_CLK_MMDC_CH0_AXI>,