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Commit 7f02f18e authored by Sekhar Nori's avatar Sekhar Nori Committed by Michael Turquette
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clk: davinci: pll-dm646x: keep PLL2 SYSCLK1 always enabled



PLL2 SYSCLK1 on DM646x is connected to DDR2 PHY and cannot
be disabled. Mark it so to prevent unused clock disable
infrastructure from disabling it.

Signed-off-by: default avatarSekhar Nori <nsekhar@ti.com>
Reviewed-by: default avatarDavid Lechner <david@lechnology.com>
Signed-off-by: default avatarMichael Turquette <mturquette@baylibre.com>
Link: lkml.kernel.org/r/20180525181150.17873-5-david@lechnology.com
parent 715478bb
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