Donate to e Foundation | Murena handsets with /e/OS | Own a part of Murena! Learn more

Commit 7d2b6ef1 authored by Linus Torvalds's avatar Linus Torvalds
Browse files

Merge tag 'armsoc-drivers' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc 

Pull ARM SoC driver updates from Olof Johansson:
 "Driver updates for v4.1.  Some of these are for drivers/soc, where we
  find more and more SoC-specific drivers these days.  Some are for
  other driver subsystems where we have received acks from the
  appropriate maintainers.

  The larger parts of this branch are:

   - MediaTek support for their PMIC wrapper interface, a high-level
     interface for talking to the system PMIC over a dedicated I2C
     interface.

   - Qualcomm SCM driver has been moved to drivers/firmware.  It's used
     for CPU up/down and needs to be in a shared location for arm/arm64
     common code.

   - cleanup of ARM-CCI PMU code.

   - another set of cleanusp to the OMAP GPMC code"

* tag 'armsoc-drivers' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc: (43 commits)
  soc/mediatek: Remove unused variables
  clocksource: atmel-st: select MFD_SYSCON
  soc: mediatek: Add PMIC wrapper for MT8135 and MT8173 SoCs
  arm-cci: Fix CCI PMU event validation
  arm-cci: Split the code for PMU vs driver support
  arm-cci: Get rid of secure transactions for PMU driver
  arm-cci: Abstract the CCI400 PMU specific definitions
  arm-cci: Rearrange code for splitting PMU vs driver code
  drivers: cci: reject groups spanning multiple HW PMUs
  ARM: at91: remove useless include
  clocksource: atmel-st: remove mach/hardware dependency
  clocksource: atmel-st: use syscon/regmap
  ARM: at91: time: move the system timer driver to drivers/clocksource
  ARM: at91: properly initialize timer
  ARM: at91: at91rm9200: remove deprecated arm_pm_restart
  watchdog: at91rm9200: implement restart handler
  watchdog: at91rm9200: use the system timer syscon
  mfd: syscon: Add atmel system timer registers definition
  ARM: at91/dt: declare atmel,at91rm9200-st as a syscon
  soc: qcom: gsbi: Add support for ADM CRCI muxing
  ...
parents 5c73cc4b 7415d97e

Documentation/devicetree/bindings/arm/atmel-at91.txt

+3 −1
Original line number Diff line number Diff line
@@ -46,10 +46,12 @@ PIT Timer required properties: 
  shared across all System Controller members.



System Timer (ST) required properties:

- compatible: Should be "atmel,at91rm9200-st"

- compatible: Should be "atmel,at91rm9200-st", "syscon", "simple-mfd"

- reg: Should contain registers location and length

- interrupts: Should contain interrupt for the ST which is the IRQ line

  shared across all System Controller members.

Its subnodes can be:

- watchdog: compatible should be "atmel,at91rm9200-wdt"



TC/TCLIB Timer required properties:

- compatible: Should be "atmel,<chip>-tcb".

Documentation/devicetree/bindings/arm/cci.txt

+5 −2
Original line number Diff line number Diff line
@@ -94,8 +94,11 @@ specific to ARM. 
		- compatible

			Usage: required

			Value type: <string>

			Definition: must be "arm,cci-400-pmu"



			Definition: Must contain one of:

				 "arm,cci-400-pmu,r0"

				 "arm,cci-400-pmu,r1"

				 "arm,cci-400-pmu"  - DEPRECATED, permitted only where OS has

						      secure acces to CCI registers

		- reg:

			Usage: required

			Value type: Integer cells. A register entry, expressed

Documentation/devicetree/bindings/bus/renesas,bsc.txt

0 → 100644
+46 −0
Original line number Diff line number Diff line 
Renesas Bus State Controller (BSC)

==================================



The Renesas Bus State Controller (BSC, sometimes called "LBSC within Bus

Bridge", or "External Bus Interface") can be found in several Renesas ARM SoCs.

It provides an external bus for connecting multiple external devices to the

SoC, driving several chip select lines, for e.g. NOR FLASH, Ethernet and USB.



While the BSC is a fairly simple memory-mapped bus, it may be part of a PM

domain, and may have a gateable functional clock.

Before a device connected to the BSC can be accessed, the PM domain

containing the BSC must be powered on, and the functional clock

driving the BSC must be enabled.



The bindings for the BSC extend the bindings for "simple-pm-bus".





Required properties

  - compatible: Must contain an SoC-specific value, and "renesas,bsc" and

		"simple-pm-bus" as fallbacks.

                SoC-specific values can be:

		"renesas,bsc-r8a73a4" for R-Mobile APE6 (r8a73a4)

		"renesas,bsc-sh73a0" for SH-Mobile AG5 (sh73a0)

  - #address-cells, #size-cells, ranges: Must describe the mapping between

		parent address and child address spaces.

  - reg: Must contain the base address and length to access the bus controller.



Optional properties:

  - interrupts: Must contain a reference to the BSC interrupt, if available.

  - clocks: Must contain a reference to the functional clock, if available.

  - power-domains: Must contain a reference to the PM domain, if available.





Example:



	bsc: bus@fec10000 {

		compatible = "renesas,bsc-sh73a0", "renesas,bsc",

			     "simple-pm-bus";

		#address-cells = <1>;

		#size-cells = <1>;

		ranges = <0 0 0x20000000>;

		reg = <0xfec10000 0x400>;

		interrupts = <0 39 IRQ_TYPE_LEVEL_HIGH>;

		clocks = <&zb_clk>;

		power-domains = <&pd_a4s>;

	};

Documentation/devicetree/bindings/bus/simple-pm-bus.txt

0 → 100644
+44 −0
Original line number Diff line number Diff line 
Simple Power-Managed Bus

========================



A Simple Power-Managed Bus is a transparent bus that doesn't need a real

driver, as it's typically initialized by the boot loader.



However, its bus controller is part of a PM domain, or under the control of a

functional clock.  Hence, the bus controller's PM domain and/or clock must be

enabled for child devices connected to the bus (either on-SoC or externally)

to function.



While "simple-pm-bus" follows the "simple-bus" set of properties, as specified

in ePAPR, it is not an extension of "simple-bus".





Required properties:

  - compatible: Must contain at least "simple-pm-bus".

		Must not contain "simple-bus".

		It's recommended to let this be preceded by one or more

		vendor-specific compatible values.

  - #address-cells, #size-cells, ranges: Must describe the mapping between

		parent address and child address spaces.



Optional platform-specific properties for clock or PM domain control (at least

one of them is required):

  - clocks: Must contain a reference to the functional clock(s),

  - power-domains: Must contain a reference to the PM domain.

Please refer to the binding documentation for the clock and/or PM domain

providers for more details.





Example:



	bsc: bus@fec10000 {

		compatible = "renesas,bsc-sh73a0", "renesas,bsc",

			     "simple-pm-bus";

		#address-cells = <1>;

		#size-cells = <1>;

		ranges = <0 0 0x20000000>;

		reg = <0xfec10000 0x400>;

		interrupts = <0 39 IRQ_TYPE_LEVEL_HIGH>;

		clocks = <&zb_clk>;

		power-domains = <&pd_a4s>;

	};

Documentation/devicetree/bindings/soc/qcom/qcom,gsbi.txt

+20 −10
Original line number Diff line number Diff line
@@ -6,7 +6,8 @@ configuration settings. The mode setting will govern the input/output mode of 
the 4 GSBI IOs.



Required properties:

- compatible: must contain "qcom,gsbi-v1.0.0" for APQ8064/IPQ8064

- compatible:	Should contain "qcom,gsbi-v1.0.0"

- cell-index:	Should contain the GSBI index

- reg: Address range for GSBI registers

- clocks: required clock

- clock-names: must contain "iface" entry
@@ -16,6 +17,8 @@ Required properties: 
Optional properties:

- qcom,crci : indicates CRCI MUX value for QUP CRCI ports.  Please reference

  dt-bindings/soc/qcom,gsbi.h for valid CRCI mux values.

- syscon-tcsr: indicates phandle of TCSR syscon node.  Required if child uses

  dma.



Required properties if child node exists:

- #address-cells: Must be 1
@@ -39,6 +42,7 @@ Example for APQ8064: 


	gsbi4@16300000 {

		compatible = "qcom,gsbi-v1.0.0";

		cell-index = <4>;

		reg = <0x16300000 0x100>;

		clocks = <&gcc GSBI4_H_CLK>;

		clock-names = "iface";
@@ -48,6 +52,8 @@ Example for APQ8064: 
		qcom,mode = <GSBI_PROT_I2C_UART>;

		qcom,crci = <GSBI_CRCI_QUP>;



		syscon-tcsr = <&tcsr>;



		/* child nodes go under here */



		i2c_qup4: i2c@16380000 {
@@ -76,3 +82,7 @@ Example for APQ8064: 
		};

	};



	tcsr: syscon@1a400000 {

		compatible = "qcom,apq8064-tcsr", "syscon";

		reg = <0x1a400000 0x100>;

	};