Merge tag 'armsoc-dt' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc

	- pclkN, clkN: Pairs of parent of input clock and input clock to the

		devices in this power domain. Maximum of 4 pairs (N = 0 to 3)

		are supported currently.

	- asbN: Clocks required by asynchronous bridges (ASB) present in

		the power domain. These clock should be enabled during power

		domain on/off operations.

- power-domains: phandle pointing to the parent power domain, for more details

		 see Documentation/devicetree/bindings/power/power_domain.txt

	"arm,arm11mp-gic"

	"brcm,brahma-b15-gic"

	"arm,arm1176jzf-devchip-gic"

	"qcom,msm-8660-qgic"

	"qcom,msm-qgic2"

- interrupt-controller : Identifies the node as an interrupt controller

- #interrupt-cells : Specifies the number of cells needed to encode an

  interrupt source.  The type shall be a <u32> and the value shall be 3.

"lacie,cloudbox"

"lacie,inetspace_v2"

"lacie,laplug"

"lacie,nas2big"

"lacie,netspace_lite_v2"

"lacie,netspace_max_v2"

"lacie,netspace_mini_v2"

QCOM Idle States for cpuidle driver

ARM provides idle-state node to define the cpuidle states, as defined in [1].

cpuidle-qcom is the cpuidle driver for Qualcomm SoCs and uses these idle

states. Idle states have different enter/exit latency and residency values.

The idle states supported by the QCOM SoC are defined as -

    * Standby

    * Retention

    * Standalone Power Collapse (Standalone PC or SPC)

    * Power Collapse (PC)

Standby: Standby does a little more in addition to architectural clock gating.

When the WFI instruction is executed the ARM core would gate its internal

clocks. In addition to gating the clocks, QCOM cpus use this instruction as a

trigger to execute the SPM state machine. The SPM state machine waits for the

interrupt to trigger the core back in to active. This triggers the cache

hierarchy to enter standby states, when all cpus are idle. An interrupt brings

the SPM state machine out of its wait, the next step is to ensure that the

cache hierarchy is also out of standby, and then the cpu is allowed to resume

execution. This state is defined as a generic ARM WFI state by the ARM cpuidle

driver and is not defined in the DT. The SPM state machine should be

configured to execute this state by default and after executing every other

state below.

Retention: Retention is a low power state where the core is clock gated and

the memory and the registers associated with the core are retained. The

voltage may be reduced to the minimum value needed to keep the processor

registers active. The SPM should be configured to execute the retention

sequence and would wait for interrupt, before restoring the cpu to execution

state. Retention may have a slightly higher latency than Standby.

Standalone PC: A cpu can power down and warmboot if there is a sufficient time

between the time it enters idle and the next known wake up. SPC mode is used

to indicate a core entering a power down state without consulting any other

cpu or the system resources. This helps save power only on that core.  The SPM

sequence for this idle state is programmed to power down the supply to the

core, wait for the interrupt, restore power to the core, and ensure the

system state including cache hierarchy is ready before allowing core to

resume. Applying power and resetting the core causes the core to warmboot

back into Elevation Level (EL) which trampolines the control back to the

kernel. Entering a power down state for the cpu, needs to be done by trapping

into a EL. Failing to do so, would result in a crash enforced by the warm boot

code in the EL for the SoC. On SoCs with write-back L1 cache, the cache has to

be flushed in s/w, before powering down the core.

Power Collapse: This state is similar to the SPC mode, but distinguishes

itself in that the cpu acknowledges and permits the SoC to enter deeper sleep

modes. In a hierarchical power domain SoC, this means L2 and other caches can

be flushed, system bus, clocks - lowered, and SoC main XO clock gated and

voltages reduced, provided all cpus enter this state.  Since the span of low

power modes possible at this state is vast, the exit latency and the residency

of this low power mode would be considered high even though at a cpu level,

this essentially is cpu power down. The SPM in this state also may handshake

with the Resource power manager (RPM) processor in the SoC to indicate a

complete application processor subsystem shut down.

The idle-state for QCOM SoCs are distinguished by the compatible property of

the idle-states device node.

The devicetree representation of the idle state should be -

Required properties:

- compatible: Must be one of -

			"qcom,idle-state-ret",

			"qcom,idle-state-spc",

			"qcom,idle-state-pc",

		and "arm,idle-state".

Other required and optional properties are specified in [1].

Example:

	idle-states {

		CPU_SPC: spc {

			compatible = "qcom,idle-state-spc", "arm,idle-state";

			entry-latency-us = <150>;

			exit-latency-us = <200>;

			min-residency-us = <2000>;

		};

	};

[1]. Documentation/devicetree/bindings/arm/idle-states.txt

The SAW2 is a wrapper around the Subsystem Power Manager (SPM) and the

Adaptive Voltage Scaling (AVS) hardware. The SPM is a programmable

micro-controller that transitions a piece of hardware (like a processor or

power-controller that transitions a piece of hardware (like a processor or

subsystem) into and out of low power modes via a direct connection to

the PMIC. It can also be wired up to interact with other processors in the

system, notifying them when a low power state is entered or exited.

Multiple revisions of the SAW hardware are supported using these Device Nodes.

SAW2 revisions differ in the register offset and configuration data. Also, the

same revision of the SAW in different SoCs may have different configuration

data due the the differences in hardware capabilities. Hence the SoC name, the

version of the SAW hardware in that SoC and the distinction between cpu (big

or Little) or cache, may be needed to uniquely identify the SAW register

configuration and initialization data. The compatible string is used to

indicate this parameter.

PROPERTIES

- compatible:

	Usage: required

	Value type: <string>

	Definition: shall contain "qcom,saw2". A more specific value should be

		    one of:

			 "qcom,saw2-v1"

			 "qcom,saw2-v1.1"

			 "qcom,saw2-v2"

			 "qcom,saw2-v2.1"

	Definition: Must have

			"qcom,saw2"

		    A more specific value could be one of:

			"qcom,apq8064-saw2-v1.1-cpu"

			"qcom,msm8974-saw2-v2.1-cpu"

			"qcom,apq8084-saw2-v2.1-cpu"

- reg:

	Usage: required

		    the register region. An optional second element specifies

		    the base address and size of the alias register region.

- regulator:

	Usage: optional

	Value type: boolean

	Definition: Indicates that this SPM device acts as a regulator device

			device for the core (CPU or Cache) the SPM is attached

			to.

Example:

Example 1:

	regulator@2099000 {

	power-controller@2099000 {

		compatible = "qcom,saw2";

		reg = <0x02099000 0x1000>, <0x02009000 0x1000>;

		regulator;

	};

Example 2:

	saw0: power-controller@f9089000 {

		compatible = "qcom,apq8084-saw2-v2.1-cpu", "qcom,saw2";

		reg = <0xf9089000 0x1000>, <0xf9009000 0x1000>;

	};